SL23EP05SI-1 Silicon Laboratories Inc, SL23EP05SI-1 Datasheet
SL23EP05SI-1
Specifications of SL23EP05SI-1
Related parts for SL23EP05SI-1
SL23EP05SI-1 Summary of contents
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Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB) Key Features • 220 MHz operating frequency range • Low output clock jitter: ⎯ 50 ps-typ cycle-to-cycle jitter ⎯ 20 ps-typ period jitter • Low output-to-output ...
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Pin Configuration Pin Description Pin Pin Name Pin Type Number 1 CLKIN Input 2 CLK2 Output 3 CLK1 Output 4 GND Power 5 CLK3 Output 6 VDD Power 7 CLK4 Output 8 CLKOUT Output Rev 2.2, June 30, 2009 8-Pin ...
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General Description The SL23EP05 is a low skew, low jitter Zero Delay Buffer with very low operating current. The product includes an on-chip high performance PLL that locks into the input reference clock and produces five (5) output clock drivers ...
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Absolute Maximum Rating Description Supply voltage, VDD All Inputs and Outputs Ambient Operating Temperature Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature ESD Rating (Human Body Model) ESD Rating (Charge Device Model) ESD Rating (Machine Model) Rev 2.2, June ...
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Operating Conditions: Unless otherwise stated VDD=2.5V to 3.3V and for both C and I Grades Symbol Description VDD3.3 3.3V Supply Voltage VDD2.5 2.5V Supply Voltage TA Operating Temperature(Ambient) CLOAD Load Capacitance CIN Input Capacitance CLBW Closed-loop bandwidth ZOUT Output Impedance ...
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DC Electrical Specifications (VDD=3.3V): Symbol Description Supply Voltage VDD Input LOW Voltage VIL Input HIGH Voltage VIH Input Leakage Current IIL Input HIGH Current IIH VOL Output LOW Voltage VOH Output HIGH Voltage Power Down Supply Current IDDPD Power Supply ...
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AC Electrical Specifications (VDD=3.3V and 2.5V) Symbol Description [1] FMAX Maximum Frequency (Input=Output ) INDC Input Duty Cycle [2] OUTDC Output Duty Cycle tr/f3.3 Rise, Fall Time (3.3V) Measured at: 0.8 to 2.0V [2] tr/f2.5 Rise, Fall Time (2.5) Measured ...
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AC Electrical Specifications (VDD=3.3V and 2.5V) Symbol Description tPLLOCK PLL Lock Time[9] [2,3] CCJ Cycle-to-cycle Jitter [2,3] PPJ Peak Period Jitter Note: 1. Typical jitter is measured at 3.3V or 2.5V, 30°C with all outputs driven into the maximum specified ...
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External Components & Design Considerations Typical Application Schematic CLKIN VDD 0.1μF Comments and Recommendations Decoupling Capacitor: A minimum decoupling capacitor of 0.1μF must be used between VDD and VSS on the pins 6 and 4. Additional capacitors may be necessary ...
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Switching Waveforms Rev 2.2, June 30, 2009 Figure 1. Output to Output Skew Figure 2. Input to Output Skew Figure 3. Part-to-Part Skew SL23EP05 Page ...
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Package Drawing and Dimensions 8-Lead SOIC (150 Mil) Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Rev 2.2, June 30, 2009 Symbol Condition θ JA Still air θ JA 1m/s air flow θ JA 3m/s ...
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Package Outline and Package Dimensions 8-Pin TSSOP Package (4.4-mm) Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Rev 2.2, June 30, 2009 Condition Still air 1m/s air flow 3m/s air flow Independent of air ...
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... Spectra Linear Inc., and an expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 2.2, June 30, 2009 Shipping Marking Package SL23EP05SC-1 Tube SL23EP05SC-1 Tape and Reel SL23EP05SI-1 Tube SL23EP05SI-1 Tape & Reel SL23EP05SC-1H Tube SL23EP05SC-1H Tape & Reel SL23EP05SI-1H Tube SL23EP05SI-1H Tape & Reel SL23EP05ZC-1 Tube ...