SL28SRC02BZI Silicon Laboratories Inc, SL28SRC02BZI Datasheet - Page 8

• Manufacturer Part Number: SL28SRC02BZI
• Description: Clock Generators & Support Products PCIE Clk Gen Xin 14M -->4 PCIE out Gen3
• Manufacturer: Silicon Laboratories Inc

Specifications of SL28SRC02BZI

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.1
Table 4. Crystal Recommendations
The SL28SRC02 requires a Parallel Resonance Crystal.
Substituting
SL28SRC02 to operate at the wrong frequency and violates
the ppm specification. For most applications there is a
300-ppm frequency shift between series and parallel crystals
due to incorrect loading
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, use the total capac-
itance the crystal sees to calculate the appropriate capacitive
loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. It is important that the trim capacitors are in
series with the crystal. It is not true that load capacitors are in
parallel with the crystal and are approximately equal to the
load capacitance of the crystal.
Calculating Load Capacitors
In addition to the standard external trim capacitors, consider
the trace capacitance and pin capacitance to calculate the
crystal loading correctly. Again, the capacitance on each side
is in series with the crystal. The total capacitance on both side
is twice the specified crystal load capacitance (CL). Trim
capacitors are calculated to provide equal capacitive loading
on both sides.
14.31818 MHz
Frequency
(Fund)
Figure 1. Crystal Capacitive Clarification
a
series
Cut
AT
resonance
Loading Load Cap
Parallel
crystal
20 pF
causes
0.1 mW
(max.)
Drive
the
Shunt Cap
,
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
Ce..................................................... External trim capacitors
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(max.)
5 pF
CLe
C s 1
Total Capacitance (as seen by the crystal)
=
Motional
0.016 pF
Figure 2. Crystal Loading Example
(max.)
C e 1
(
Load Capacitance (each side)
Ce1 + Cs1 + Ci1
X 1
C i1
Ce = 2 * CL - (Cs + Ci)
C lo c k C h ip
1
X T A L
Tolerance
using standard value trim capacitors
35 ppm
(max.)
C i2
(lead frame, bond wires, etc.)
+
X 2
1
C e 2
Ce2 + Cs2 + Ci2
SL28SRC02
Stability
30 ppm
(max.)
C s 2
1
Page 8 of 14
3 to 6 p
3 3 p F
P in
T r im
2 .8 p F
T r a c e
F
Aging
(max.)
5 ppm
)