CY28RS480ZXC Silicon Laboratories Inc, CY28RS480ZXC Datasheet
CY28RS480ZXC
Specifications of CY28RS480ZXC
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CY28RS480ZXC Summary of contents
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Features ® • Supports AMD CPU • 200 MHz differential CPU clock pairs • 100 MHz differential SRC clocks • 48 MHz USB clock • 33 MHz PCI clock • 66 MHz HyperTransport™ clock Block Diagram XIN XTAL OSC XOUT ...
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Pin Description Pin No. Name 41,40,45,44 CPUT/C 50 PCI0 37 IREF 52, 53, 54 REF[2:0] 7 SCLK 8 SDATA 27, 28, 30, 29 SRCST/C[1:0] 12, 13, 16, SRCT/C[5:0] 17, 18, 19, 22, 23, 24, 25, 34, 33 10,11 CLKREQ#[0:1] 4 ...
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Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The ...
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Table 3. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit Description 18:11 Command Code – 8 bits 19 Acknowledge from slave 27:20 Data byte – 8 bits 28 Acknowledge from slave 29 Stop Control Registers Byte 0:Control ...
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Byte 2: Control Register 2 Bit @Pup Name 7 1 CPUT/C SRCT USB_48 5 1 PCI 4 0 Reserved 3 1 Reserved 2 0 CPU SRC 1 1 Reserved 0 1 Reserved Byte 3: Control Register 3 Bit ...
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Byte 4: Control Register 4 (continued) Bit @Pup Name 0 1 Reserved Byte 5: Control Register 5 Bit @Pup Name 7 0 SRC[T/C SRC[T/C SRC[T/C SRC[T/C SRC[T/C SRC[T/C ...
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Table 4. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap 14.31818 MHz AT Parallel Crystal Recommendations The CY28RS480 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28RS480 to operate at the wrong frequency and violate ...
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CLK_REQ[0:1]# Description The CLKREQ#[1:0] signals are active low input used for clean stopping and starting selected SRC outputs. The outputs controlled by CLKREQ#[1:0] are determined by the settings in register bytes 4 and 5. The CLKREQ# signal is a debounced ...
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Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DDA V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J ESD ESD Protection (Human Body Model) HBM Ø ...
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AC Electrical Specifications Parameter Description Crystal T XIN Duty Cycle DC T XIN Period PERIOD XIN Rise and Fall Times XIN Cycle to Cycle Jitter CCJ L Long-term Accuracy ACC CPU Outputs T /T ...
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AC Electrical Specifications (continued) Parameter Description T Duty Cycle Slew Rate Cycle to Cycle jitter CCJ T HTT66 clock to PCI clock Skew SKEW PCI T PCI Duty Cycle DC T Spread Disabled PCI ...
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Test and Measurement Set-up For PCI Single-ended Signals and Reference The following diagram shows the test load configurations for the single-ended PCI, USB, and REF output signals. PCI/ USB REF For Differential CPU and SRC Output Signals The following diagram ...
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... Ordering Information Part Number Lead-free CY28RS480OXC 56-pin SSOP CY28RS480OXCT 56-pin SSOP – Tape and Reel CY28RS480ZXC 56-pin TSSOP CY28RS480ZXCT 56-pin TSSOP – Tape and Reel Package Drawing and Dimensions 56-Lead Shrunk Small Outline Package O56 28 29 0.720 0.730 0.088 0.092 ...
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Package Drawing and Dimensions 56-Lead Thin Shrunk Small Outline Package, Type mm) Z56 0.249[0.009 13.894[0.547] 14.097[0.555] 0.851[0.033] 0.500[0.020] 0.950[0.037] BSC While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear ...