Si5330K-A00227-GM Silicon Laboratories Inc, Si5330K-A00227-GM Datasheet - Page 10
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Si5330K-A00227-GM
Manufacturer Part Number
Si5330K-A00227-GM
Description
Clock Generators & Support Products Sngl-End 2.5v LVPECL 4-out, 5 to 350 MHz
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI5330D-A00212-GM.pdf
(20 pages)
Specifications of Si5330K-A00227-GM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Si5330
5. Pin Descriptions—Si5330
Note: Center pad must be tied to GND for normal operation.
10
Pin #
1
2
3
4
5
6
RSVD_GND
RSVD_GND
RSVD_GND
Pin Name
IN1
IN2
IN3
I/O
I
I
I
RSVD_GND
RSVD_GND
RSVD_GND
Table 9. Si5330 Pin Descriptions
IN2
IN3
IN1
Signal Type
Multi
Multi
Multi
7
24
8
Rev. 0.35
23
9
GND
22
Si5330A/B/C/G/H/J Differential Input Devices.
These pins are used as the differential clock input. IN1 is
the positive input; IN2 is the negative input. Refer to
“AN408: Termination Options for Any-Frequency, Any-
Output Clock Generators and Clock Buffers—Si5338,
Si5334, Si5330” for interfacing and termination details.
Si5330F/K/L/M Single-Ended Input Devices.
These pins are not used. Leave IN1 unconnected and
IN2 connected to ground.
Si5330F/K/L/M Single-Ended Devices.
This is the single-ended clock input. Refer to AN408 for
interfacing and termination details.
Si5330A/B/C/G/H/J Differential Input Devices.
This pin is not used. Connect to ground.
Ground.
Must be connected to system ground.
Ground.
Must be connected to system ground.
Ground.
Must be connected to system ground.
GND
10
21
11
20
12
19
CLK1A
CLK1B
VDDO1
VDDO2
CLK2A
CLK2B
Description