SPL505YC256BTT Silicon Laboratories Inc, SPL505YC256BTT Datasheet - Page 14

• Manufacturer Part Number: SPL505YC256BTT
• Description: Clock Generators & Support Products CK505 v0.85
• Manufacturer: Silicon Laboratories Inc

Specifications of SPL505YC256BTT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.4 March 21, 2007
PD# Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300 µs of PD# deassertion to a voltage greater than
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used to
synchronously stop and start the CPU output clocks while the
rest of the clock generator continues to function. When the
CPU_STP# pin is asserted, all CPU outputs that are set with
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCT 100MHz
USB, 48MHz
PCI, 33MHz
DOT96C
DOT96T
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCT 100MHz
PCI, 33 MHz
USB, 48MHz
PD#
REF
DOT96C
DOT96T
REF
PD#
Figure 3. PD Assertion Timing Waveform
PD Deassertion Timing Waveform
Tdrive_PW RDN#
<300µS, >200mV
Tstable
<1.8ms
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Below is an example showing the relationship of
clocks coming up.
the SMBus configuration to be stoppable via assertion of
CPU_STP# are stopped within two to six CPU clock periods
after being sampled by two rising edges of the internal CPUC
clock. The final states of the stopped CPU signals are CPUT
= HIGH and CPUC = LOW.
SPL505YC256BT/
SPL505YC256BS
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