CY28401OCT Silicon Laboratories Inc, CY28401OCT Datasheet
CY28401OCT
Specifications of CY28401OCT
Related parts for CY28401OCT
CY28401OCT Summary of contents
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MHz Differential Buffer for PCI Express and SATA Features • CK409 or CK410 companion buffer • Eight differential 0.7V clock pairs • Individual OE controls • Low CTC jitter (< 50 ps) • Programmable bandwidth • SRC_STOP# power management ...
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Pin Description Pin 4,5 SRCT_IN, SRCC_IN 8,9,12,13,16,17,20,21,29,30, DIFT/C(7:0) 33,34,37,38,41,42 6,7,14,15,35,36,43,44 OE_(7:0) 28 HIGH_BW# 45 LOCK 26 PWRDWN# 1 SRC_DIV/2# 27 SRC_STOP# 23 SCLK 24 SDATA 46 IREF 22 PLL/BYPASS# 48 VDD_A 47 VSS_A 3,10,18,25,32,40 VSS 2,11,19,31,39 VDD Serial Data Interface ...
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Table 2. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Description 10 Acknowledge from slave 11:18 Command Code – 8 bits '00000000' stands for block operation 19 Acknowledge from slave 20:27 Byte Count from master – 8 ...
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Byte 0: Control Register 0 (continued) Bit @pup Name Byte 1: Control Register 1 Bit @pup Name ...
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Byte 2: Control Register 2 (continued) Bit @pup Name Byte 3: Control Register 3 Bit @pup Name ...
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PWRDWN# Clarification The PWRDWN# pin is used to shut off all clocks cleanly and instruct the device to evoke power savings mode. Additionally, PWRDWN# should be asserted prior to shutting off the input clock or power to ensure all ...
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S1 Delay >0.25ms S0 Power Off SRC_STOP# Clarification The SRC_STOP# signal is an active LOW input used for clean stopping and starting the DIFT/C outputs (valid clock must be present on SRCT/C_IN). The SRC_STOP# signal is a debounced signal in ...
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SRC_STOP# PWRDWN# DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 5. SRC_STOP# =Driven, PWRDWN# = Three-state SRC_STOP# PWRDWN# DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 6. SRC_STOP# =Three-state, PWRDWN# = Driven SRC_STOP# PWRDWN# DIFT(Free Running DIFC(Free Running ...
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OE Assertion (Transition from ‘0’ to ‘1’) All differential outputs that were three-stated will resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2–6 DIF clock periods. In addition, DIFT clocks ...
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Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction to Case JC Ø Dissipation, ...
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AC Electrical Specifications (continued) Parameter Description V Voltage Low LOW V Crossing Point Voltage at 0.7V Swing OX ΔV Vcross Variation over all edges OX V Maximum Overshoot Voltage OVS V Minimum Undershoot Voltage UDS V Ring Back Voltage RB ...
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... V OVS V RB Figure 10. Single-ended Measurement Points for V Skew Management Point 0.000V Figure 11. Differential (Clock-CLock#) Measurement Points (Tperiod, Duty Cycle and Jitter) Ordering Information Ordering Code CY28401OC CY28401OCT Lead-Free CY28401OXC CY28401OXCT Rev 1.0, November 21, 2006 LOW V UDS ,V OVS UDS T PERIOD High Duty Cycle % ...
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Package Drawing and Dimensions While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir- cuitry or for the infringement of any patents or other rights of third ...