SL28610BLCT Silicon Laboratories Inc, SL28610BLCT Datasheet - Page 14

• Manufacturer Part Number: SL28610BLCT
• Description: Clock Generators & Support Products AtomPoulsbo Handheld Embed.1.5V PCIe G1
• Manufacturer: Silicon Laboratories Inc

Specifications of SL28610BLCT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
Table 1. Output Driver Status during PCI_STPPCI_STP# and CPU_STP#
Note: *Differential clocks output state can be configured through Byte 19 bits 3:.0
...................... DOC #: SP-AP-0078 (Rev. AA) Page 14 of 23
Single-ended Clocks Stoppable
Differential Clocks
CPU_STP#
CPUC Internal
CPUT Internal
CPU_STP#
CPUT
CPUC
Non stoppable
Stoppable
Non stoppable
CPUT
CPUC
Figure 4. CPU_STP# Assertion Waveform
Figure 5. CPU_STP# Deassertion Waveform
Running
Running
Clock driven high
Clock# driven low
Running
CPU_STP# Asserted
Tdrive_CPU_STP#,10 ns>200 mV
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the
deassertion to active outputs is no more than two CPU clock
cycles.
.
.
Driven low
Driven Low
SMBus Disabled
Driven low
Clock driven high*
Clock# driven low*
OE# Pins Disabled
SL28610