PI6C185-01QIE Pericom Semiconductor, PI6C185-01QIE Datasheet - Page 3

• Manufacturer Part Number: PI6C185-01QIE
• Description: Clock Buffer Precision 1:5 Clock Driver
• Manufacturer: Pericom Semiconductor

Specifications of PI6C185-01QIE

• Number Of Outputs: 5
• Propagation Delay (max): 5.5 ns
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
2-Wire I
The I
output and test mode enable.
The PI6C185-01 is a slave receiver device. It can not be read back.
Sub-addressing is not supported. All preceding bytes must be sent
in order to change one of the control bytes.
Every bite put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving
device.
During normal data transfers SDATA changes only when SCLK is
LOW. Exceptions: A HIGH-to-LOW transition on SDATA while
SCLK is HIGH indicates a “start” condition. A LOW-to-HIGH
transition on SDATA while SCLK is HIGH is a “stop” condition
and indicates the end of a data transfer cycle.
Maximum Ratings
(Above which the useful life may be impaired.
For user guidelines, not tested.)
Supply Current (V
Storage Temperature ...................................... –65°C to +150°C
Ambient Temperature with Power Applied ....... –40°C to +85°C
3.3V Supply Voltage to Ground Potential ........... –0.5V to +4.6V
DC Input Voltage .............................................. –0.5V to +4.6V
S
y
I
I
I
I
m
D
D
D
D
2
D
D
D
D
b
C interface permits individual enable/disable of each clock
l o
08-0298
S
S
S
S
u
u
u
u
2
p p
p p
p p
p p
C Control
P
a
y l
y l
y l
y l
a r
C
C
C
C
m
r u
r u
r u
r u
t e
e r
e r
e r
e r
r e
t n
t n
t n
t n
DD
= +3.465V, C
B
B
B
B
U
U
U
U
F
F
F
F
_
_
_
_
N I
N I
N I
N I
e T
=
=
=
=
t s
0
6
1
1
. 6
0 0
3 3
C
M
6 6
o
0 .
3 .
H
n
LOAD
d
z
M
M
M
t i
o i
H
H
H
z
z
z
n
= Max.)
M
. n i
T
3
1
2
0 7
y
0 2
0 0
Each data transfer is initiated with a start condition and ended with
a stop condition. The first byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addressed device, LOW = write to addressed device). If the device’s
own address is detected, PI6C185-01 generates an acknowledge
by pulling SDATA line LOW during ninth clock pulse, then
accepts the following data bytes until another start or stop condition
is detected.
Following acknowledgement of the address byte (0D2H), two
more bytes must be sent:
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
Note:
Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
. p
1. “Command Code” byte, and
2. “Byte Count” byte.
M
3
a
. x
U
m
n
A
s t i
Precision 1-5 Clock Buffer
PI6C185-01
PS8318F
11/13/08
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5