Si5338Q-A-GM Silicon Laboratories Inc, Si5338Q-A-GM Datasheet
Si5338Q-A-GM
Specifications of Si5338Q-A-GM
Related parts for Si5338Q-A-GM
Si5338Q-A-GM Summary of contents
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GRA UAD LOCK ENERATOR Features Low power MultiSynth™ technology enables independent, any-frequency synthesis on four differential output drivers Highly-configurable output drivers with up to ...
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Si5338 Functional Block Diagram Osc noclk P1DIV_IN IN1 IN2 ÷P1 IN3 P2DIV_IN IN4 ÷P2 IN5 noclk IN6 Control & Memory OEB/PINC/FINC I2C_LSB/PDEC/FDEC NVM Control SCL (OTP) SDA INTR 2 VDD Synthesis Stage 1 (PLL) ref Loop Phase VCO Filter Frequency ...
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T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Si5338 1. Electrical Specifications Table 1. Recommended Operating Conditions (V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol Ambient Temperature T A Core Supply Voltage V DD Output Buffer Supply V ...
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Table 3. DC Characteristics (V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Core Supply Current Output Buffer Supply Current Notes: 1. Single CMOS driver active. 2. Measured into a 5” 50 ...
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Si5338 Table 5. Performance Characteristics (V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol PLL Acquisition Time PLL Tracking Range PLL Loop Bandwidth MultiSynth Frequency Synthesis Resolution CLKIN Loss of Signal ...
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Table 5. Performance Characteristics (Continued 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol Phase Increment/Decrement P Update Time Frequency Increment/ Decrement Step Size MultiSynth range for frequency increment/decrement Frequency Increment/ ...
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Si5338 Table 6. Input and Output Clock Characteristics (V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol Input Clock (AC Coupled Differential Input Clocks on Pins IN1/2, IN5/6) Frequency f IN ...
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Table 6. Input and Output Clock Characteristics (Continued 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol V OC HCSL Output Voltage V SEPP Rise/Fall Time ...
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Si5338 Table 7. Control Pins (V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Input Control Pins (IN3, IN4) Input Voltage Low Input Voltage High Input Capacitance Input Resistance Output Control Pins ...
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Table 10. Crystal Specifications for MHz Parameter Crystal Frequency Load Capacitance (on-chip differential) Crystal Output Capacitance Equivalent Series Resistance Crystal Max Drive Level Table 11. Crystal Specifications for MHz Parameter Crystal Frequency Load Capacitance ...
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Si5338 1,2,3 Table 12. Jitter Specifications (V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol GbE Random Jitter J 4 (12 kHz–20 MHz) GbE Random Jitter R (1.875–20 MHz) OC-12 Random ...
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Table 12. Jitter Specifications (V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol Random Jitter (12 kHz–20 MHz) Deterministic Jitter Total Jitter J (See Note (12 kHz–20 ...
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Si5338 Table 13. Typical Phase Noise Performance Offset Frequency 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 2 Table 14 Specifications (SCL,SDA) Parameter Symbol Test Condition LOW Level V ILI2C Input Voltage HIGH Level ...
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Typical Application Circuits +3.3 V 0.1 uF Power Supply Decoupling Capacitors (1 per VDD or VDDOx pin) Optional XTAL for 27 MHz Free-run Applications XTAL 27 MHz Single-ended or 74.25 MHz Differential Inputs 74.25/1.001 MHz for Synchronous 148.5 MHz ...
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Si5338 3. Functional Description Osc CLKIN IN1 IN2 ÷P1 IN3 FDBK IN4 ÷P2 IN5 IN6 Control & Memory OEB/PINC/FINC I2C_LSB/PDEC/FDEC NVM Control SCL (OTP) SDA INTR 3.1. Overview The Si5338 is a high-performance, low-jitter clock generator capable of synthesizing four ...
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Input Stage The input stage supports four inputs. Two are used as the clock inputs to the synthesis stage, and the other two are used as feedback inputs for zero delay or external feedback mode. In cases where external ...
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Si5338 Synthesis of the output clocks is performed in two stages, as shown in Figure 5. The first stage consists of a high-frequency analog phase-locked loop (PLL) that multiplies the input stage to a frequency within the range of 2.2 ...
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Output Stage The output stage consists of output selectors, output dividers, and programmable output drivers as shown in Figure 7. Output Stage ÷ R0 ÷ R1 ÷ R2 ÷ R3 Figure 7. Output Stage The output selectors select the ...
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Si5338 3.5.1. Ordering a Custom NVM Configuration The Si5338 is orderable with a factory-programmed custom NVM configuration. This is the simplest way of using the Si5338 since it generates the desired output frequencies at power-up or after a power-on reset ...
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Disable Outputs Set OEB_ALL = 1; reg230[4] Pause LOL Set DIS_LOL = 1; reg241[7] Write new configuration to device Register accounting for the write-allowed mask Map (See AN411) Use ClockBuilder Desktop v3.0 or later Validate input clock status Input clocks ...
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Si5338 3.5.4. Modifying a MultiSynth Output Divider Ratio/ Frequency Configuration The output MultiSynth dividers of a configured and phase-locked Si5338 can be modified without relocking the PLL (i.e. without following section 3.5.3). This feature allows any of the four output ...
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Control & Memory NVM Control (OTP Enabled OEB 1 = Disabled Figure 12. Output Enable Pin (Si5338K/L/M) 3.7.2. Enabling Outputs through the I Output enable can be controlled through the I interface. As shown in Figure 13, register ...
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Power Consumption The Si5338 Power consumption is a function of Supply voltage Frequency of output Clocks Number of output Clocks Format of output Clocks Because of internal voltage regulation, the current from the core V ...
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Reset Options There are two types of resets on the Si5338, POR and soft reset. A POR reset automatically occurs whenever the supply voltage on the VDD is applied. The soft reset is forced by writing 0x02 to register ...
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Si5338 3.10.4. Output Synchronization Upon power soft_reset the Si5338 synchronizes the output clocks. With normal output polarity (no output clock inversion), the Si5338 synchronizes the output clocks to the falling, not rising edge. Synchronization at the rising ...
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Relative Frequency Figure 16. Configurable Spread Spectrum 4. Applications of the Si5338 Because of its ...
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Si5338 4.2. Synchronous Frequency Translation In other cases useful to generate an output frequency that is synchronous (or phase-locked) to another clock frequency. The Si5338 is the ideal choice for generating up to four clocks with different frequencies ...
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I C Interface Configuration and operation of the Si5338 is controlled by reading and writing to the RAM space using the I interface. The device operates in slave mode with 7-bit addressing and can operate (100 kbps) or ...
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Si5338 6. Si5338 Registers For many applications, the Si5338's register values are easily configured using ClockBuilder Desktop (see "3.1.1. ClockBuilder™ Desktop Software" on page 16). However, for customers interested in using the Si5338 in operating modes beyond the capabilities available ...
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Pin Descriptions Note: Center pad must be tied to GND for normal operation. Pin # Pin Name I/O Signal Type 1,2 IN1/IN2 I Top View IN1 1 CLK1A IN2 CLK1B ...
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Si5338 Table 15. Si5338 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Type 3 IN3 I 4 IN4 I 32 This pin can have one of the following functions depending on the part number: CLKIN (for Si5338A/B/C and Si5338N/P/Q ...
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Table 15. Si5338 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Type 5,6 IN5/IN6 I Multi 7 VDD VDD Supply 8 INTR O Open Drain 9 CLK3B O Multi 10 CLK3A O Multi 11 VDDO3 VDD Supply 12 SCL ...
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Si5338 Table 15. Si5338 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Type 15 VDDO2 VDD Supply 16 VDDO1 VDD Supply 17 CLK1B O 18 CLK1A O 19 SDA I/O LVCMOS 20 VDDO0 VDD Supply 21 CLK0B O 22 ...
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... SCL SCL CLK2B CLK2B CLK2A CLK2A VDDO2 VDDO2 VDDO1 VDDO1 Rev. 1.0 Si5338 Si5338K: 710 MHz Si5338N: 710 MHz Si5338L: 350 MHz Si5338P: 350 MHz Si5338M: 200 MHz Si5338Q: 200 MHz 1 1 CLKIN CLKIN 1 1 CLKINB CLKINB 2 OEB CLKIN 3 I2C_LSB FDBK 4 4 ...
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... CLK0B CLK0B CLK0A CLK0A GND GND VDD VDD Rev. 1.0 Si5338K: 710 MHz Si5338N: 710 MHz Si5338L: 350 MHz Si5338P: 350 MHz Si5338M: 200 MHz Si5338Q: 200 MHz CLK1B CLK1B CLK1A CLK1A SDA SDA VDDO0 VDDO0 CLK0B CLK0B CLK0A CLK0A GND ...
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Package Outline: 24-Lead QFN Figure 25. 24-Lead Quad Flat No-lead (QFN) Dimension aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. ...
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Si5338 10. Recommended PCB Layout Dimension Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is ...
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Top Marking Line Characters Line 1 Si5338 Line 2 Xxxxxx Line 3 RTTTTT Circle with 0.5 mm diameter; left-justified Line 4 YYWW Si5338 Xxxxxx RTTTTT YYWW Figure 26. Si5338 Top Marking Table 19. Top Marking Explanation Description Base part ...
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... MHz to 200 MHz OEB Pin Control + I2C_LSB Si5338N - 0.16 MHz to 710 MHz Four Inputs (2 Differential, 2 Single-ended) Si5338P - 0.16 MHz to 350 MHz Four Inputs (2 Differential, 2 Single-ended) Si5338Q - 0.16 MHz to 200 MHz Four Inputs (2 Differential, 2 Single-ended) Evaluation Boards Si5338 Si5338/56 40 GMR AXXXXX Operating Temp Range: -40 to +85 ° ...
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OCUMENT HANGE IST Revision 0.1 to 0.2 Updated block diagram to show Rn output divider and PLL bypass mode Updated pin description to include FDBK± Updated Table 3. DC Characteristics Updated Table 12. ...
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