DS1077U-66 Maxim Integrated Products, DS1077U-66 Datasheet - Page 9
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DS1077U-66
Manufacturer Part Number
DS1077U-66
Description
Timers & Support Products EconOscillator-Divid onOscillator-Divider
Manufacturer
Maxim Integrated Products
Datasheet
1.DS1077Z-125TR.pdf
(21 pages)
DATA TRANSFER ON 2-WIRE SERIAL BUS Figure 2
Figure 2 details how data transfer is accomplished on the 2-wire bus. Depending upon the state of the
R/
1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released.
The DS1077 may operate in the following two modes:
1) Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is
2) Slave transmitter mode: The first byte is received and handled as in the slave receiver mode.
W
master is the slave address. Next, follows a number of data bytes. The slave returns an acknowledge
bit after each received byte.
transmitted by the master. The slave then returns an acknowledge bit. Next, follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned.
received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is performed by hardware after the slave
address and direction bit have been received.
However, in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data
is transmitted on SDA by the DS1077 while the serial clock is input on SCL. START and STOP
conditions are recognized as the beginning and end of a serial transfer.
bit, two types of data transfer are possible:
SDA
SCL
CONDITION
START
MSB
1
2
slave address
6
7
direction
R/W
8
bit
9 of 21
signal from receiver
acknowledgement
ACK
9
1
2
repeated if more bytes
are transferred
3 - 8
8
signal from receiver
acknowledgement
ACK
9
START CONDITION
STOP CONDITION
REPEATED
OR