NJU6356EM NJR, NJU6356EM Datasheet - Page 4
![Real Time Clock Serial I/O Real Time Clock](/photos/16/0/160046/dmp8_sml.jpg)
NJU6356EM
Manufacturer Part Number
NJU6356EM
Description
Real Time Clock Serial I/O Real Time Clock
Manufacturer
NJR
Datasheet
1.NJU6356EM-TE1.pdf
(6 pages)
Specifications of NJU6356EM
Function
Clock, Calendar, Timer, Alarm, Low Battery Detect
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 80 C
Minimum Operating Temperature
- 30 C
Mounting Style
SMD/SMT
Rtc Bus Interface
Serial
Package / Case
DMP-8
Time Format
HH:MM:SS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NJU6356EM
Manufacturer:
JRC
Quantity:
289
Company:
Part Number:
NJU6356EM-TE2
Manufacturer:
NEC
Quantity:
2 500
Part Number:
NJU6356EM-TE2
Manufacturer:
JRC
Quantity:
20 000
NJU6356
3. Timer Data Writing
and the timer data can be written to the NJU6356.
clock signal input from the CLK terminal, and the data is transferred from the shift register to the timer counter by
synchronized with falling edge of the CE signal. In this time the second-counter is cleared to "0", and the oscillator
divider start the operation.
< Write Down Timing >
4. Low Voltage Detector
(EE)
5. Data Access
5V±10%. It may be broken the data unless 5V±10%.
operation.
- 4 -
When both of the I/O terminal and the CE terminal are "H", update is stopped, the oscillator divider is cleared,
The timer data is written into the shift register from the DATA terminal by synchronized with rising edge of the
The input data strings are LSB first of each digit as shown below.
The NJU6356 series incorporate the low battery detector. If the supply voltage reduce to the detection level,
The NJU6356 series can operate from 2.0V to 5.5V. However, it is not allow the data access out of the range of
Thus, when the data access, the CE terminal should be "H" after the power supply rise to 5V±10%, then start the
Shift
Register
Data
Input
CLK
CE
H
I/O
is written into each digit of the shift register as warning code for the CPU.
Note) When the CE signal is which rising edge or falling edge,
Type E
The data is read out from LSB of Year, and last 44-bit is effective.
the CLK signal should be fixed to "L". And so, before the
CE signal is raised, the I/O signal should be fixed to "H".
0
Year
0
The data is input into the shift
register at rising edge of the
CLK.
1
1
Month
2
2
3
Year
3
4
Day
4
5
5
Days of
Week
6
6
7
The data in the shift register is
transferred to the timer counter at this
falling edge of the CE, then the
oscillator divider start the operation.
7
Hour
Minute
3
3
Minute
4
4
Second
5
5
6
6
7
7