MC10EP195FA ON Semiconductor, MC10EP195FA Datasheet - Page 16

• Manufacturer Part Number: MC10EP195FA
• Description: Delay Lines / Timing Elements 3.3V ECL
• Manufacturer: ON Semiconductor

Specifications of MC10EP195FA

• Function: Active Programmable Delay Line
• Supply Voltage (min): +/- 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): +/- 3.6 V
• Package / Case: LQFP-32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Multi−Channel Deskewing
channel delay matching. Slight differences in impedance and
cable length can create large timing skews within a high−speed
system. To deskew multiple signal channels, each channel can
Measure Unknown High Speed Device Delays
unknown delay of a device with a high degree of precision.
By combining two EP195s and EP31 as shown in Figure 9,
the delay can be measured. The first EP195 can be set to
SETMIN and its output is used to drive the unknown delay
device, which in turn drives the input of a D flip−flop of
EP31. The second EP195 is triggered along with the first
EP195 and its output provides a clock signal for EP31.
The programmed delay of the second EP195 is varied to
detect the output edge from the unknown delay device.
CLOCK
CLOCK
The most practical application for EP195 is in multiple
EP195s provide a possible solution to measure the
Control
Logic
IN
IN
IN
IN
Control
Logic
EP195
EP195
Digital
Data
#1
#2
Figure 8. Multiple Channel Deskewing Diagram
Figure 9. Multiple Channel Deskewing Diagram
IN
IN
IN
IN
IN
IN
Q
Q
Q
Q
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EP195
EP195
EP195
16
#N
#1
#2
Unknown Delay
be sent through each EP195 as shown in Figure 8. One signal
channel can be used as reference and the other EP195s can be
used to adjust the delay to eliminate the timing skews. Nearly
any high−speed system can be fine−tuned (as small as 10 ps)
to reduce the skew to extremely tight tolerances.
long, the flip−flop output will be at logic high. On the other
hand, if the programmed delay through the second EP195 is
too short, the flip−flop output will be at a logic low. If the
programmed delay is correctly fine−tuned in the second
EP195, the flip−flop will bounce between logic high and logic
low. The digital code in the second EP195 can be directly
correlated into an accurate device delay.
If the programmed delay through the second EP195 is too
Device
Q
Q
Q
Q
Q
Q
D
CLK
EP31
Q
Q