DS1374U-3 Maxim Integrated Products, DS1374U-3 Datasheet - Page 5

• Manufacturer Part Number: DS1374U-3
• Description: Real Time Clock
• Manufacturer: Maxim Integrated Products

Specifications of DS1374U-3

• Function: Clock, Calendar, Elapsed Time Counter, Watchdog Timekeeper
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial
• Package / Case: uSOP
• Time Format: Binary
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER-UP/POWER-DOWN CHARACTERISTICS
(T
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when the device is in write protection.
Note 2: Limits at -40°C are guaranteed by design and not production tested.
Note 3: All voltages are referenced to ground.
Note 4: V
Note 5: The use of the 250Ω trickle-charge resistor is not allowed at V
Note 6: Measured at V
Note 7: Measured at V
Note 8: Measured at V
Note 9: SCL only.
Note 10: SDA and SQW and INT.
Note 11: The RST pin has an internal 50kΩ pullup resistor to V
Note 12: Trickle charger disabled.
Note 13: I
Note 14: Specified with I
Note 15: Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
Note 16: WDSTR = 1. BBSQW = 1 is required for operation when V
Note 17: C
Note 18: After this period, the first clock pulse is generated.
Note 19: The maximum t
Note 20: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V
Note 21: A fast-mode device can be used in a standard-mode system, but the requirement t
Note 22: Guaranteed by design. Not production tested.
Note 23: The parameter t
Note 24: This delay applies only if the oscillator is enabled and running. If the EOSC bit is 1, the startup time of the oscillator is
V
(V
V
V
V
V
A
CC
CC
PF(MIN)
CC
PF(MAX)
CC
= -40°C to +85°C) (Figure 3)
Detect to Recognize Inputs
Fall Time; V
Rise Time; V
Rising)
nal) to bridge the undefined region of the falling edge of SCL.
automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low
period of the SCL signal, it must output the next data bit to the SDA line t
the SCL line is released.
0V ≤ V
added to this delay.
PARAMETER
CCA
I
BACKUP
B
—total capacitance of one bus line in pF.
2
—SCL clocking at max frequency = 400kHz.
C, 32-Bit Binary Counter Watchdog RTC with
CC
PF(MAX)
PF(MIN)
should not exceed V
≤ V
CC MAX
CC
CC
CC
2
HD:DAT
to
to
OSF
C bus inactive.
= typ, V
= typ, V
= typ, V
Trickle Charger and Reset Input/Output
is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
and 1.3V ≤ V
only has to be met if the device does not stretch the low period (t
BACKUP
BACKUP
BACKUP
SYMBOL
t
RPU
CC
t
t
R
F
_____________________________________________________________________
MAX or 3.7V, whichever is greater.
BACKUP
= 0V, register 09h = A5h.
= 0V, register 09h = A6h.
= 0V, register 09h = A7h.
(Note 24)
≤ 3.7V.
CC
CONDITIONS
.
CC
is below the power-fail trip point (or absent).
CC
> 3.63V and should not be enabled.
R
max + t
SU:DAT
SU:DAT
MIN
300
LOW
0
= 1000 + 250 = 1250ns before
≥ to 250ns must be met. This is
) of the SCL signal.
TYP
250
IHMIN
MAX
of the SCL sig-
UNITS
ms
μs
μs
5