MC10EL34D ON Semiconductor, MC10EL34D Datasheet - Page 6

• Manufacturer Part Number: MC10EL34D
• Description: Clock Generators & Support Products 5V ECL Clock
• Manufacturer: ON Semiconductor

Specifications of MC10EL34D

• Mounting Style: SMD/SMT
• Package / Case: SOIC-16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLK
CLK
MR
MR
EN
EN
Q0
Q1
Q2
Q0
Q1
Q2
There are two distinct functional relationships between the Master Reset and Clock:
The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The internal
divider flip−flops will maintain their state during the freeze. The EN is deasserted (LOW), and after the next falling edge
of CLK, then the internal divider flip−flops will “unfreeze” and continue to their next state count with proper phase rela-
tionships.
OUTPUT
CLOCK
MR
T
RR
CASE 2: If the MR is de−asserted (H−L), after the Clock has transitioned low, the
CASE 1
CASE 1: If the MR is de−asserted (H−L), while the Clock is still high, the
outputs will follow the second ensuing clock rising edge.
outputs will follow the first ensuing clock rising edge.
Figure 3. Reset Recovery Time
Figure 2. Timing Diagrams
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OUTPUT
6
CLOCK
MR
T
RR
Internal Clock
Internal Clock
Disabled
Disabled
CASE 2
Internal Clock
Internal Clock
Enabled
Enabled