MC100LVEL32DR2 ON Semiconductor, MC100LVEL32DR2 Datasheet

Clock Drivers & Distribution 3.3V ECL Divide By 2

MC100LVEL32DR2

Manufacturer Part Number
MC100LVEL32DR2
Description
Clock Drivers & Distribution 3.3V ECL Divide By 2
Manufacturer
ON Semiconductor
Datasheet

Specifications of MC100LVEL32DR2

Mounting Style
SMD/SMT
Package / Case
SOIC-8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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MC100LVEL32
3.3V ECL ÷2 Divider
Description
functionally identical to the EL32, but operates from a 3.3 V supply.
Upon power-up, the internal flip-flop will attain a random state; the
reset allows for the synchronization of multiple LVEL32’s in a system.
this device only. For single-ended input conditions, the unused
differential input is connected to V
V
and V
to 0.5 mA. When not used, V
Features
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 10
BB
The MC100LVEL32 is an integrated ÷2 divider. The LVEL32 is
The reset pin is asynchronous and is asserted on the rising edge.
The V
V
V
For Additional Information, see Application Note AND8003/D
Oxygen Index: 28 to 34
510 ps Propagation Delay
2.6 GHz Typical Maximum Frequency
ESD Protection: Human Body Model; >4 kV,
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range:
NECL Mode Operating Range:
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
Flammability Rating: UL 94 V−0 @ 0.125 in,
Transistor Count = 111 devices
Pb−Free Packages are Available
CC
CC
may also rebias AC coupled inputs. When used, decouple V
CC
= 3.0 V to 3.8 V with V
= 0 V with V
BB
via a 0.01 mF capacitor and limit current sourcing or sinking
pin, an internally generated voltage supply, is available to
EE
Machine Model; >200 V
= −3.0 V to −3.8 V
BB
EE
should be left open.
BB
= 0 V
as a switching reference voltage.
1
BB
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
CASE 506AA
CASE 948R
MN SUFFIX
*For additional marking information, refer to
DT SUFFIX
CASE 751
D SUFFIX
TSSOP−8
8
(Note: Microdot may be in either location)
Application Note AND8002/D.
SOIC−8
8
DFN8
ORDERING INFORMATION
1
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
http://onsemi.com
Publication Order Number:
DIAGRAMS*
8
1
MARKING
8
1
MC100LVEL32/D
ALYWG
1
KVL32
ALYW
KV32
G
G
4

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MC100LVEL32DR2 Summary of contents

Page 1

MC100LVEL32 3.3V ECL ÷2 Divider Description The MC100LVEL32 is an integrated ÷2 divider. The LVEL32 is functionally identical to the EL32, but operates from a 3.3 V supply. The reset pin is asynchronous and is asserted on the rising edge. Upon ...

Page 2

Reset 1 R CLK 2 ÷2 CLK Figure 1. Logic Diagram and Pinout Assessment Table 2. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input ...

Page 3

Table 3. LVPECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Output ...

Page 4

Table 5. AC CHARACTERISTICS V Symbol Characteristic f Maximum Toggle Frequency max t Propagation Delay CLK to Q (Differential) PLH t CLK to Q (Single−Ended) PHL t Reset Recovery RR t Minimum Pulse Width Reset PW t Random Clock Jitter ...

Page 5

... ORDERING INFORMATION Device MC100LVEL32D MC100LVEL32DG MC100LVEL32DR2 MC100LVEL32DR2G MC100LVEL32DT MC100LVEL32DTG MC100LVEL32DTR2 MC100LVEL32DTR2G MC100LVEL32MNR4 MC100LVEL32MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D ...

Page 6

... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

Page 7

K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) D −T− G SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...

Page 8

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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