ETHER-1GQD-O4-B1 Lattice, ETHER-1GQD-O4-B1 Datasheet
ETHER-1GQD-O4-B1
Specifications of ETHER-1GQD-O4-B1
Related parts for ETHER-1GQD-O4-B1
ETHER-1GQD-O4-B1 Summary of contents
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... Lever TM CORE CORE 10/100 and 1Gig Ethernet Media Access Controller User’s Guide March 2006 ipug09_05.0 ...
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... The Ethernet MAC transmits and receives data between a host processor and an Ethernet network. The main func- tion of the Ethernet MAC is to ensure that the Media Access rules specified in the 802.3 IEEE standard are met while transmitting a frame of data over Ethernet. Figure 2 shows the transmission of data on the Ethernet network 10/100 and 1Gig Ethernet Media Access Controller User’ ...
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... The Receive MAC checks the address of the received packet and validates whether the frame can be received before transferring it onto the FIFO. Only valid frames are transferred into the FIFO. This feature has the following two benefits; the systems need not re-calculate the Frame Check Sequence (FCS) again when the frame is being transmitted, and it also keeps the receive MAC relatively simple ...
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... Lattice Semiconductor Signal Descriptions Table 1. Tri-Speed Ethernet MAC Input and Output Signals Port Name Clocks and Reset sys_clk rx_appclk gtx_clk tx_clk rx_clk mdc reset_n Host Interface hcs_n haddr[7:0] hdatain[((datawidth-1):0] hwrite_n hread_n hready_n hdataout_en_n hdataout[(datawidth-1):0] Transmit MAC Application Interface tx_fifodata[15:0] Media Access Controller User’ ...
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... Lattice Semiconductor Table 1. Tri-Speed Ethernet MAC Input and Output Signals (Continued) Port Name tx_fifobyten[1:0] tx_fifoavail tx_fifoeof tx_fifoempty tx_sndpaustim[15:0] tx_sndpausreq tx_fifoctrl tx_staten tx_macread tx_statvec[30:0] tx_done Media Access Controller User’s Guide Active Type State Input N/A Transmit FIFO Read Data Byte Enable . The upper bit validates the upper byte of the transmitted data ...
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... Lattice Semiconductor Table 1. Tri-Speed Ethernet MAC Input and Output Signals (Continued) Port Name tx_discfrm Management Interface Signals mdi mdo mdio_en G/MII Signals txd[7:0] txen txer rxdv rxd[7:0] rxer col crs Receive MAC Application Interface rx_fifo_full rx_write rx_dbout[15:0] rx_byten[1:0] rx_stat_vector[31:0] rx_stat_en Media Access Controller User’s Guide ...
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... It is qualified by rx_eof. Default 1000 Mbps This parameter defines the Ethernet speed the core will support. The Mode terms “1000 Mbps Mode” and “Gigabit Mode” are used interchange- ably in this document. “10/100 Mbps Mode” and “Fast Mode” are also used interchangeably ...
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... PHY device. In this case, the divided clock is output to the FIFO interface as rx_appclk. The output signals from the Rx MAC interface are synchronous to this clock. The Rx MAC is disabled while reset_n is low and should only be enabled after the associated registers are prop- erly initialized. 10/100 and 1Gig Ethernet Media Access Controller User’s Guide 8 ...
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... MAC_ADDR_1 and MAC_ADDR_2 registers. Filtering based on Frame Length The default minimum Ethernet frame size is 64 bytes. Any frame smaller than 64 bytes could possibly be a collision fragment. By default, the Rx MAC is configured to ignore bytes shorter than 64 bytes. The user can configure the MAC to receive shorter frames by setting bit [8] of the TX_RX_CTL register ...
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... VLAN Tag Detected. This bit is set when the Tri-Speed MAC receives a VLAN Tagged frame. 15:0 Frame Byte Count. This contains the length of the frame that was received. The frame length includes the DA, SA, L/T, TAG, DATA, PAD and FCS fields. 10/100 and 1Gig Ethernet Media Access Controller User’s Guide Description 10 ...
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... The DA, SA, L/T, and DATA fields are derived from higher applications through the FIFO interface and then encap- sulated into an Un-tagged Ethernet frame. This frame is not sent over the network until the network has been idle for a minimum of Inter Packet Gap (IPG) time. The Frame encapsulation consists of adding the Preamble bits, the Start of Frame Data (SFD) bits and the CRC check sum to the end of the frame (FCS) ...
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... In the 10/100 mode, the Tx MAC provides the following information: • Whether the frame deferred before transmission • The number of times the frame experiences collision before transmission. This information is sent as a part of the statistics vector. For a frame transmitted without any errors, the statistics vector, qualifi ...
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... Table 4 lists the Tri-Speed MAC registers accessible via the Host Interface. The registers are either Read/Write (R/W) or Read Only (RO) for status reporting purposes. The values of the registers immediately after the Reset Condition is removed from the Tri-Speed MAC (POR Value in Hexadecimal format) are also given. 10/100 and 1Gig Ethernet Media Access Controller User’s Guide 13 ...
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... Tx MAC either to pause or to transmit a PAUSE frame. 0 Gigabit Enable. In Gigabit mode, this bit is always high and cannot be overwritten. In 10/100 Gbit_en mode, this bit is always low and cannot be overwritten. 10/100 and 1Gig Ethernet Media Access Controller User’s Guide Mnemonic I/O Address MODE ...
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... Promiscuous Mode. When asserted, all filtering schemes are abandoned and the Rx MAC receives frames with any address. Maximum size of the packet than can be handled by the core. Reserved. Inter-packet gap value in units of bit time. 15 10/100 and 1Gig Ethernet Description Description Description ...
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... Mnemonic: MAC_ADD POR Value = 0000H. The MAC Address Registers 0-2 contain the Ethernet address of the port. The MAC Address Register [0] has the two bytes that are transmitted first and the MAC Address Register [2] has the two bytes that are transmitted last. ...
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... Mnemonic: MLT_TAB_[0-7] POR Value = 0000H. When the core is programmed to receive multicast frames, a filtering scheme is used to decide whether the frame should be received or not. The six middle bits of the most significant byte of the CRC value, calculated for the des- tination address, are used as a key to the 64-bit hash table. The three most significant bits select one of the eight tables, and the three least signifi ...
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... Reception of a 64-Byte Frame Without Error -Rx MAC Application Interface (Gigabit Mode) Figure 3. Reception of a 64-byte Frame Without Error rx_appclk rx_byte_en[1:0] rx_dbout[15:0] rx_write rx_stat_en rx_stat_vector[31:0] rx_eof rx_error rx_fifo_error Media Access Controller User’s Guide PAUSE Opcode. 11 1,2 3,4 5,6 18 10/100 and 1Gig Ethernet Description 59,60 61,62 63,64 Valid ...
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... Figure 5. Reception of a 64-byte Frame with FIFO Overflow rx_appclk rx_byte_en[1:0] rx_dbout[15:0] rx_write rx_stat_en rx_stat_vector[31:0] rx_eof rx_error rx_fifo_full rx_fifo_error Media Access Controller User’s Guide 11 1,2 3,4 5,6 59,60 61,62 63,64 11 1,2 3,4 5,6 59,60 61,62 63,64 19 10/100 and 1Gig Ethernet Valid Valid ...
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... The signal tx_done is asserted to indicate a successful transmission. This is shown in Figure 6. Figure 6. Transmission of a 64-Byte Frame without Error sine_tx_clk sine_tx_firame_ready tx_fifobyten[1:0] tx_fifodata[15:0] tx_macread tx_staten tx_staten[31:0] tx_fifoeof tx_fifoempty tx_discfrm tx_done Media Access Controller User’s Guide 11 11 1,2 3,4 59,60 61,62 63,64 20 10/100 and 1Gig Ethernet 0 0 Valid ...
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... The frame is transmitted as a valid frame and tx_done is asserted at the end of transmission. Figure 7. Successful Transmission of a 64-byte Frame with FIFO Empty tx_clk tx_fifoavail tx_fifobyten[1:0] tx_fifodata[15:0] tx_macread tx_staten tx_staten[31:0] tx_fifoeof tx_fifoempty tx_discfrm tx_done Media Access Controller User’s Guide 11 11 59,60 61,62 63,64 1,2 3,4 21 10/100 and 1Gig Ethernet 0 0 Valid ...
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... The frame transmission is abandoned when this occurs. Figure 8. Aborted Transmission Due to FIFO Empty tx_clk tx_fifoavail tx_fifobyten[1:0] tx_fifodata[15:0] tx_macread tx_staten tx_staten[31:0] tx_fifoeof tx_fifoempty tx_discfrm tx_done Media Access Controller User’s Guide 11 11 1,2 3,4 59,60 61,62 63,64 22 10/100 and 1Gig Ethernet 0 0 Valid ...
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... Figure 10. Management Interface Read and Write Operations mdc mdio_en mdo address and write data mdi Media Access Controller User’s Guide ADDR A ADDR DATA A WRITE OPERATION address of register being read WRITE OPERATION 23 10/100 and 1Gig Ethernet B DATA B READ OPERATION read data READ OPERATION ...
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... Media Access Controller User’s Guide VALID FRAME DATA FRAME WITHOUT ERROR VALID FRAME DATA FRAME WITHOUT ERROR 24 10/100 and 1Gig Ethernet VALID FRAME DATA FRAME WITH ERROR VALID FRAME DATA FRAME WITH ERROR ...
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... North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Media Access Controller User’s Guide VALID FRAME DATA FRAME WITHOUT COLLISION VALID FRAME DATA FRAME WITHOUT ERROR 25 10/100 and 1Gig Ethernet VALID FRAME DATA FRAME WITH COLLISION VALID FRAME DATA FRAME WITH ERROR ...
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... ORCA 4 family, performance may vary. Supplied Netlist Configurations The Ordering Part Number (OPN) for all 1000Mbps configurations of this core on ORCA Series 4 is ETHER-1GIG- 04-N3. The Ordering Part Number (OPN) for all 10/100Mbps configurations of this core on ORCA Series 4 is ETHER-FAST-04-N3. Table 5 lists the netlist confi ...
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... The Ordering Part Number (OPN) for all 1000Mbps configurations of this core on ispXPGA is ETHER-1GIG-XP- N3. The Ordering Part Number (OPN) for all 10/100Mbps configurations of this core on ORCA ispXPGA is ETHER- FAST-XP-N3. Table 6 lists the netlist configurations that are available in the Evaluation Package for this core, which can be downloaded from the Lattice web site at www.latticesemi.com. You can use the IPexpress software tool to help generate new confi ...
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... The Ordering Part Number (OPN) for all 1000Mbps configurations of this core on LatticeECP/EC is ETHER-1GIG- E2-N3. The Ordering Part Number (OPN) for all 10/100Mbps configurations of this core on LatticeECP/EC is ETHER-FAST-E2-N3. Table 7 lists the netlist configurations that are available in the Evaluation Package for this core, which can be downloaded from the Lattice web site at www.latticesemi.com. ...
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... The Ordering Part Number (OPN) for all 1000Mbps configurations of this core on LatticeXP is ETHER-1GIG-XM- N3. The Ordering Part Number (OPN) for all 10/100Mbps configurations of this core on LatticeXP is ETHER-FAST- XM-N3. Table 8 lists the netlist configurations that are available in the Evaluation Package for this core, which can be downloaded from the Lattice web site at www.latticesemi.com. You can use the IPexpress software tool to help generate new confi ...
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... The Ordering Part Number (OPN) for all 1000Mbps configurations of this core on LatticeSC is ETHER-1GIG-SC- N3. The Ordering Part Number (OPN) for all 10/100Mbps configurations of this core on LatticeSC is ETHER-FAST- SC-N3. Table 9 lists the netlist configurations that are available in the Evaluation Package for this core, which can be downloaded from the Lattice web site at www.latticesemi.com. You can use the IPexpress software tool to help generate new confi ...