MAX3353EEUE Maxim Integrated Products, MAX3353EEUE Datasheet - Page 11

• Manufacturer Part Number: MAX3353EEUE
• Description: Communication ICs - Various
• Manufacturer: Maxim Integrated Products
• Type: USB On-the-Go Charge Pumpr

Specifications of MAX3353EEUE

• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V
• Supply Type: Analog
• Package / Case: TSSOP-16
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.6 V
• Supply Current: 73 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 5. Start and Stop Conditions
bidirectional communication between master(s) and
slave(s). A master (typically a microcontroller) initiates
all data transfers to and from the MAX3353E and gen-
erates the SCL clock that synchronizes the data trans-
fer (Figure 4).
The MAX3353E SDA line operates as both an input and
an open-drain output. A pullup resistor (4.7kΩ typ) is
required on SDA. The MAX3353E SCL line operates
only as an input. A pullup resistor (4.7kΩ typ) is
required on SCL if there are multiple masters on the 2-
wire interface, or if the master in a single-master system
has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 5) sent by a master, followed by the MAX3353E
7-bit slave address plus R/W bit (Figure 6), a register
address byte, one or more data bytes, and finally a
STOP condition (Figure 5).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning the SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 5).
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high (Figure 7).
The acknowledge bit is the clocked ninth bit that the
recipient uses to handshake receipt of each byte of
data (Figure 8). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
SDA
SCL
CONDITION
START
USB On-the-Go Charge Pump with Switchable
S
______________________________________________________________________________________
Start and Stop Conditions
Acknowledge
Bit Transfer
CONDITION
STOP
P
Pullup/Pulldown Resistors
the master is transmitting to the MAX3353E, the
MAX3353E generates the acknowledge bit because it
is the recipient. When the MAX3353E is transmitting to
the master, the master generates the acknowledge bit
because the master is the recipient.
The MAX3353E has a 7-bit-long slave address. The
eighth bit following the 7-bit slave address is the R/W
bit. It is low for a write command, high for a read com-
mand. The first 6 bits (MSBs) of the MAX3353E slave
address are always 010110. Select slave address bit
A0 by connecting the address input ADD to V
or leave floating (ADD is internally pulled to GND
through a 110kΩ resistor). The MAX3353E has two pos-
sible slave addresses (Table 1). As a result, only two
MAX3353E devices can share the same interface.
A write to the MAX3353E comprises the transmission of
the MAX3353E’s slave address with the R/W bit set to
zero, followed by 2 bytes of information. The first byte
of information is the command byte that determines
which register of the MAX3353E is to be written by the
second byte. The second byte is the data that goes into
the register that is set by the first byte. Figure 9 shows
the typical write byte format.
A read from the MAX3353E comprises the transmission
of the MAX3353E’s slave address (from the master)
with the R/W bit set to zero, followed by one byte con-
taining the address of the register, from which the mas-
ter is going to read data, and then followed by
MAX3353E’s slave address again with the R/W bit set
to one. After that one byte of data is being read by the
master. Figure 10 shows the read byte format that must
be used. To read many contiguous registers, multiple
accesses are required.
There are two read/write control registers. Control reg-
ister 1 is used to set D+, D- pullup or pulldown, and to
set interrupt output to open-drain or push-pull. Control
register 2 is the bus control register used to control the
bus operation and put the device into shutdown mode.
(Tables 3, 4, and 5.)
The status register is a read-only register for determining
valid bus and session comparator thresholds, ID_IN sta-
tus, and HNP success. Tables 6 and 7 show status regis-
ter address map, bit configuration, and description.
Control Registers (10h, 11h)
Write Byte Format
Read Byte Format
Status Register (13h)
Slave Address
Registers
L
, GND,
11