DS2172TN/T&R Maxim Integrated Products, DS2172TN/T&R Datasheet - Page 6

• Manufacturer Part Number: DS2172TN/T&R
• Description: Communication ICs - Various
• Manufacturer: Maxim Integrated Products
• Type: Bit Error Rate Testerr

Specifications of DS2172TN/T&R

• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Supply Type: Analog
• Package / Case: TQFP-32
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current: 10 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.0 PARALLEL CONTROL INTERFACE
The DS2172 is controlled via a multiplexed bi-directional address/data bus by an external microcontroller
or microprocessor. The DS2172 can operate with either Intel or Motorola bus timing configurations. If
the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All
Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C. Electrical
Characteristics for more details. The multiplexed bus on the DS2172 saves pins because the address
information and data information share the same signal paths. The addresses are presented to the pins in
the first portion of the bus cycle and data will be transferred on the pins during second portion of the bus
cycle. Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS2172 latches
the address from the AD0 to AD7 pins. Valid write data must be present and held stable during the later
portion of the DS or
portion of the DS or
state as
also be easily connected to non-multiplexed buses. RCLK and TCLK are used to update counters and
load transmit and receive pattern registers. At slow clock rates, sufficient time must be allowed for these
port operations.
3.0 PATTERN SET REGISTERS
The Pattern Set Registers (PSR) are loaded each time a new pattern (whether it be pseudorandom or
repetitive) is to be generated. When a pseudorandom pattern is generated, all four PSRs must be loaded
with FF Hex. When a repetitive pattern is to be created, the four PSRs are loaded with the pattern that is
to be repeated. Please see Tables 4 and 5 for some programming examples.
PATTERN SET REGISTERS
4.0 PATTERN LENGTH REGISTER
Length Bits LB4 to LB0 determine the length of the pseudorandom polynomial or programmable
repetitive pattern that is generated and detected. With the pseudorandom patterns, the “Tap A” feedback
position of the pattern generator is always equal to the value in the Pattern Length Register (PLR). Please
refer to Figure 2 for a block diagram of the pattern generator and to Tables 4 and 5 for some
programming examples.
PLR: PATTERN LENGTH REGISTER (Address=04 Hex)
(MSB)
PS31
PS23
PS15
(MSB)
PS7
-
RD
PS30
PS22
PS14
PS6
transitions high in Intel timing or as DS transitions low in Motorola timing. The DS2172 can
-
PS29
PS21
PS13
PS5
RD
WR
pulses. The read cycle is terminated and the bus returns to a high impedance
pulses. In a read cycle, the DS2172 outputs a byte of data during the latter
PS28
PS20
PS12
PS4
-
PS27
PS19
PS11
PS3
LB4
PS26
PS18
PS10
PS2
6 of 22
LB3
PS25
PS17
PS9
PS1
(LSB)
PS24
PS16
PS8
PS0
LB2
PSR3 (addr.=00 Hex)
PSR2 (addr.=01 Hex)
PSR1 (addr.=02 Hex)
PSR0 (addr.=03 Hex)
LB1
(LSB)
LB0
DS2172