DS26528-W Maxim Integrated Products, DS26528-W Datasheet - Page 171

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DS26528-W

Manufacturer Part Number
DS26528-W
Description
Network Controller & Processor ICs Octal E1-T1-J1 Singl e-Chip Transceiver (
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS26528-W

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS26528-W
Manufacturer:
Maxim Integrated
Quantity:
10 000
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 5: Receive FIFO Overrun (ROVR).
Bit 4: Receive HDLC Opening Byte Event (RHOBT).
Bit 3: Receive Packet-End Event (RPE).
Bit 2: Receive Packet-Start Event (RPS).
Bit 1: Receive FIFO Above High Watermark Set Event (RHWMS).
Bit 0: Receive FIFO Not Empty Set Event (RNES).
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
7
0
RIM5
Receive Interrupt Mask Register 5 (HDLC)
0A4h + (200h x n): where n = 0 to 7, for Ports 1 to 8
6
0
ROVR
5
0
RHOBT
171 of 276
4
0
RPE
3
0
DS26528 Octal T1/E1/J1 Transceiver
RPS
2
0
RHWMS
1
0
RNES
0
0

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