DS21448-LW Maxim Integrated Products, DS21448-LW Datasheet - Page 24

• Manufacturer Part Number: DS21448-LW
• Description: Network Controller & Processor ICs 3.3V Quad E1-T1-J1 L ine Interface T1-E1-
• Manufacturer: Maxim Integrated Products

Specifications of DS21448-LW

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The bits in the SR register have the unique ability to initiate a hardware interrupt through the INT output pin. Each
of the alarms and events in the SR can be either masked or unmasked from the interrupt pin through the interrupt
mask register (IMR). The interrupts caused by the RCL, RUA1, and LOTC bits in the SR act differently than the
interrupts caused by the other status bits in the SR. The RCL, RUA1, and LOTC bits forces the INT pin low
whenever they change state (i.e., go active or inactive). The INT pin is allowed to return high (if no other interrupts
are present) when the user reads the alarm bit that caused the interrupt to occur, even if the alarm is still present.
The other status bits in the SR can force the INT pin low when they are set. The INT pin is allowed to return high (if
no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
The host can quickly determine which of the four LIU channels is generating an interrupt by reading one of the
unused addresses in the 16h–1Fh range in any LIU channel. See the following LIU channel interrupt status
description for additional information.
LIU Channel Interrupt Status
(MSB)
SR (06H): Status Register
(Real Time)
(Real Time)
(Real Time)
(Real Time)
(Latched)
(Latched)
(Latched)
(Latched)
PRBSD
NAME
NAME
TOCD
LOTC
RUA1
TCLE
(MSB)
LIU4
LIU3
LIU2
LIU1
LUP
LDN
RCL
N/A
N/A
N/A
N/A
LUP
—
POSITION
POSITION
SR.7
SR.6
SR.5
SR.4
SR.3
SR.2
SR.1
SR.0
7
6
5
4
3
2
1
0
LDN
—
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
LIU4 Status Register. A 1 in this bit position indicates that the status register (SR) in channel 4 is
asserting an interrupt.
LIU3 Status Register. A 1 in this bit position indicates that the status register (SR) in channel 3 is
asserting an interrupt.
LIU2 Status Register. A 1 in this bit position indicates that the status register (SR) in channel 2 is
asserting an interrupt.
LIU1 Status Register. A 1 in this bit position indicates that the status register (SR) in channel 1 is
asserting an interrupt.
Loop-Up Code Detected. This bit is set when the loop-up code defined in registers RUPCD1 and
RUPCD2 is being received. See Section
Loop-Down Code Detected. This bit is set when the loop-down code defined in registers
RDNCD1 and RDNCD2 is being received. See Section
Loss-of-Transmit Clock. This bit is set when the TCLK pin has not transitioned for 5µs (±2µs),
forcing the LOTC pin high.
Receive Unframed All Ones. This bit is set when an unframed all-ones code is received at RRING
and RTIP
Receive Carrier Loss. This bit is set when an RCL condition exists at RRING and RTIP. See
(Table
Transmit Current-Limit Exceeded. This bit is set when the 50mA (RMS) current limiter is activated
whether or not the current limiter is enabled.
Transmit Open-Circuit Detect. This bit is set when the device detects that the TTIP and TRING
outputs are open circuited.
PRBS Detect. This bit is set when the receive side detects a 2
pseudorandom bit sequence (PRBS).
LOTC
5-A) for details.
—
(Table
5-A).
RUA1
—
24 of 60
LIU4
RCL
6.1
FUNCTION
FUNCTION
for details.
TCLE
6.1
LIU3
for details.
15
- 1 (E1) or a QRSS (T1)
TOCD
LIU2
PRBSD
(LSB)
(LSB)
LIU1