DS3154 Maxim Integrated Products, DS3154 Datasheet
DS3154
Specifications of DS3154
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DS3154 Summary of contents
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... GENERAL DESCRIPTION The DS3151 (single), DS3152 (dual), DS3153 (triple), and DS3154 (quad) line interface units (LIUs) perform the functions necessary for interfacing at the physical layer to DS3, E3, or STS-1 lines. Each LIU has independent receive and transmit paths and a built-in jitter attenuator. ...
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... RECEIVER........................................................................................................................22 7. TRANSMITTER ................................................................................................................25 8. DIAGNOSTICS .................................................................................................................28 9. JITTER ATTENUATOR ....................................................................................................29 10. RESET LOGIC..................................................................................................................30 11. TRANSFORMERS............................................................................................................31 12. JTAG TEST ACCESS PORT AND BOUNDARY SCAN ..................................................32 13. ELECTRICAL CHARACTERISTICS ................................................................................37 14. PIN ASSIGNMENTS.........................................................................................................46 15. PACKAGE INFORMATION ..............................................................................................59 16. THERMAL INFORMATION ..............................................................................................60 17. REVISION HISTORY ........................................................................................................61 DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs TABLE OF CONTENTS ...
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... Figure 14-4. DS3152 CPU Bus Mode Pin Assignment.............................................................................54 Figure 14-5. DS3153 Hardware Mode Pin Assignment............................................................................55 Figure 14-6. DS3153 CPU Bus Mode Pin Assignment.............................................................................56 Figure 14-7. DS3154 Hardware Mode Pin Assignment............................................................................57 Figure 14-8. DS3154 CPU Bus Mode Pin Assignment.............................................................................58 DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs LIST OF FIGURES ...
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... Table 13-H. CPU Bus Timing ...................................................................................................................40 Table 13-I. JTAG Interface Timing ...........................................................................................................45 Table 14-A. Pin Assignments Sorted by Signal Name .............................................................................46 Table 14-B. Pin Assignments Sorted by Pin Number ...............................................................................48 Table 16-A. Thermal Properties, Natural Convection ...............................................................................60 Table 16-B. Theta-JA (θ ) vs. Airflow ......................................................................................................60 JA DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs LIST OF TABLES ...
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... Output driver monitor 1. DETAILED DESCRIPTION The DS3151 (single), DS3152 (dual), DS3153 (triple), and DS3154 (quad) LIUs perform the functions necessary for interfacing at the physical layer to DS3, E3, or STS-1 lines. Each LIU has independent receive and transmit paths and a built-in jitter attenuator. The receiver performs clock and data recovery from a B3ZS- or HDB3-coded alternate mark inversion (AMI) signal and monitors for loss of the incoming signal ...
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... Business TeleCommunications; 34Mbps Digital Unstructured and Structured Lease Lines; TBR 24 Attachment Requirements for Terminal Equipment Interface, 1997 GR-253-CORE SONET Transport Systems: Common Generic Criteria, Issue 2, December 1995 Transport Systems Generic Requirements (TSGR): Common Requirements, Issue 1, GR-499-CORE December 1998 DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs SPECIFICATION TITLE ANSI ITU-T ETSI TELCORDIA ...
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... Shorthand Notations. The notation “DS315x” throughout this data sheet refers to either the DS3151, DS3152, DS3153, or DS3154. This data sheet is the specification for all four parts. The LIUs on the DS315x are identical. For brevity, this document uses the pin name and register name shorthand “NAMEn,” where “n” stands in place of the LIU port number ...
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... Automatic Gain RXPn Control + Adaptive RXNn Equalizer Analog Local Loopback TDMn Driver Monitor TXPn TXNn Loopback Control TTSn LLBn DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs RJAn Clock & Data Recovery Remote ALOS Loopback squelch Digital Local Loopback RLBn TJAn TLBOn TBIN RLOSn RBIN ...
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... Gain RXPn Control + Adaptive Equalizer RXNn ALOS Analog Local Loopback TDMn Driver Monitor TXPn TXNn Loopback Control TTSn DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs RLOSn STMCLK Digital LOS Dallas Detector Semiconductor DS315x B3ZS/HDB3 Decoder Clock & Data Recovery Remote Loopback squelch Digital Local ...
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... INT O Note: In CPU bus mode, status/control pins are replaced by register bits. See Register Map in Section 5. For pin names of the form PINn LIU PIN1 is on LIU 1, PIN2 is on LIU 2, etc. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs FUNCTION TRANSMITTER Transmitter Clock Transmitter Positive AMI/Transmitter Data ...
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... Transmitter Jitter Attenuator Enable 0 = remove jitter attenuator from the transmitter path TJAn insert jitter attenuator into the transmitter path (Note that TJA = 1 takes precedence over RJA = 1.) DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs FUNCTION 7 for additional details. 1-1). These outputs can be tri-stated using the TTS (Figure ...
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... Receiver Jitter Attenuator Enable 0 = remove jitter attenuator from the receiver path RJAn insert jitter attenuator into the receiver path (Note that TJA = 1 takes precedence over RJA = 1.) DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs FUNCTION (Figure 1-1). 6 for additional details ...
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... Chip Select (Active Low). CS must be asserted in order to read or write internal registers. I Write Enable (Active Low) or Read/Write Select. In Intel bus mode (MOT = 0 asserted R/W I write internal registers. In Motorola bus mode (MOT = 1), R/W determines the type of bus DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs FUNCTION 3 for details loopback 01 = remote loopback ...
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... TDSB can be configured to transmit a pattern in the new operating mode. Table 4-G. Receiver PRBS Pattern Select Options E3M STS Rx MODE DS3 1 1 STS-1 DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs FUNCTION signals should be wired together. DD signals should be wired together. SS FUNCTION STS Tx MODE X Any 0 DS3 0 ...
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... TEST Note 1: Underlined bits are read-only; all other bits are read-write. Note 2: The registers are named REGn, where n = the LIU number ( 4). Note 3: The bit names are the same for each LIU register set. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs BIT 7 BIT 6 BIT 5 BIT 4 ...
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... Bit 0: Reset (RST). When this bit is high, the digital logic of the LIU is held in reset and all registers for that LIU (except the RST bit) are forced to their default values. RST is cleared power-up and when the RST pin is activated normal operation 1 = reset LIU DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs REAL-TIME STATUS ON WRITE LOGIC 1 OTHER INT SOURCE ...
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... Bit 1: Transmitter Line Build-Out (TLBO). TLBO indicates cable length for waveform shaping in DS3 and STS-1 modes. TLBO is ignored in E3 mode cable length ≥ 225ft 1 = cable length < 225ft DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs TCRn Transmitter Configuration Register 01h, 11h, 21h, 31h 5 ...
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... Bit 0: Receive Code-Violation Counter Update (RCVUD). When this control bit transitions from low to high, the RCVLn and RCVHn registers are loaded with the current code-violation count, and the internal code-violation counter is cleared. 0→1 = Update RCV registers and clear internal code-violation counter DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs RCRn Receiver Configuration Register 02h, 12h, 22h, 32h ...
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... PLL is not locked onto the incoming signal Bit 0: Receiver Loss of Signal (RLOS). This read-only status bit indicates the current state of the receiver loss-of- signal detector signal present 1 = loss of signal DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs SRn Status Register 03h, 13h, 23h, 33h 5 ...
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... RLOSL is cleared when the host processor writes a one to it and is not set again until RLOS changes state again. When RLOSL is set, it can cause a hardware interrupt to occur if the RLOSIE interrupt-enable bit is set to one. The interrupt is cleared when RLOSL is cleared or RLOSIE is set to zero. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs SRLn Status Register Latched ...
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... RCVUD control bit is toggled low to high. After the RCV registers are updated, the line-code violation counter is cleared. The counter operates in two modes, depending on the setting of the ITU bit in the RCR register. See the RCR register description for details about the ITU control bit. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs SRIEn Status Register Interrupt Enable ...
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... RLOS when it counts 175 ±75 consecutive zeros coming out of the CDR block and clears RLOS when it counts 175 ±75 consecutive pulse intervals without excessive zero occurrences. The requirements of ITU-T G.775 for E3 LOS defects are met by a combination of the ALOS detector and the DLOS detector, as follows: DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs Figure 1-1 shows the ...
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... Hardware mode or ITU bit set to 0 – A BPV immediately preceded by a valid pulse ( valid pulse and a zero (B, 0, V). – A BPV with the same polarity as the last BPV. – The fourth zero in an EXZ occurrence (only in hardware mode or when ITU = 0). DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs ...
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... Receiver Jitter Tolerance. The receiver exceeds the input jitter tolerance requirements of all applicable telecommunication standards in Table Figure 6-1. Receiver Jitter Tolerance 15 DS3 GR-499 Cat II 10 DS3 GR-499 Cat I 1.0 0.1 10 DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 1-A. See Figure 6-1. STS-1 GR253 10 5 1.5 E3 G.823 30 300 669 2 ...
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... When the transmitter is tri-stated, the transmit driver monitor is also disabled. The transmitter is declared to be faulty when the transmitter outputs see a load of less than ~25Ω. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs Figure 7-2 for the structure of the DS3 AIS signal. The TDSA and TDSB input ...
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... T ≤ 1.4 -0.85 ≤ T ≤ -0.36 -0.36 ≤ T ≤ +0.36 0.36 ≤ T ≤ 1.4 Governing Specifications: Bellcore GR-253 and Bellcore GR-499 and ANSI T1.102. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs Table NORMALIZED AMPLITUDE EQUATION UPPER CURVE 0.03 0 sin[(π / 2)( 0.34)]} + 0.03 ...
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... DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs SPECIFICATION 51.840Mbps (±20ppm) B3ZS Coaxial cable (AT&T 734A or equivalent) At the end 450ft of coaxial cable 75Ω (±1%) resistive 0.800V nominal (not covered in specs) An isolated pulse (preceded by two zeros and followed by one or more zeros) falls within the curved listed in Between -1 ...
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... PRBS pattern. A change of state of the PRBS bit can cause an interrupt on the INT pin if the PRBSIE interrupt-enable bit is set to one. A pattern bit error can also cause an interrupt if the PBERIE interrupt-enable bit is set to one. The PRBS detector also declares sync in the presence of an incoming all-ones pattern. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs ...
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... If the signal on the MCLK pin is toggling, the JA uses the signal on the MCLK pin as its master clock. If the MCLK pin is high, the JA uses the signal on the TCLK pin as its master clock. When enabled in the transmit path, DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs Figure 3-1 ...
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... LIU, including resetting the LIU’s registers to the default state (except for the RST bit). The POR signal and RST pin require an active master clock source for the LIU to properly reset. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 1k DS3 [GR-499 (1995)] ...
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... Halo Electronics 1 Note: Table subject to change. Industrial temperature range and other multiples (dual, quad) are also available. Contact the manufacturers for details at www.pulseeng.com and www.haloelectronics.com. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs VALUE 1:2ct ±2% 19μH (min) 0.150μH (max) 10pF (max) 1500V (min) ...
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... Section 4. Details about the boundary scan architecture and the TAP can be found in IEEE 1149.1- 1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994. Figure 12-1. JTAG Block Diagram 10k DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs Figure 12-1 Bypass Register Boundary Scan Register Device Identification Register ...
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... On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is low or to the Exit1-DR state if JTMS is high. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 1 Select ...
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... Update-IR. The instruction shifted into the instruction shift register is latched into the parallel output on the falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS low puts the controller in the Run-Test-Idle state. With JTMS high, the controller enters the Select-DR-Scan state. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs ...
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... JTDI and JTDO. The outputs do not change during the CLAMP instruction. Table 12-B. JTAG ID Code PART REVISION DS3154 Consult factory DS3153 Consult factory DS3152 Consult factory DS3151 Consult factory DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs INSTRUCTION CODES 010 Bypass 111 000 Bypass 011 Bypass 100 001 DEVICE CODE ...
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... I/O cells. DS315x BSDL files are available at www.maxim-ic.com/TechSupport/telecom/bsdl.htm. Identification Register. This register contains a 32-bit shift register and a 32-bit latched parallel output selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs ...
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... O Note 1: TCLKn = STMCLK = 51.84MHz; TXPn/TXNn driving all ones into 75Ω resistive loads; analog loopback enabled; all other inputs grounded; all other outputs open. Note 2: TCLKn = STMCLK = 51.84MHz; other inputs at V Note 3: 0V < V < DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs (except SYMBOL CONDITIONS V IH ...
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... Note 11: Outputs loaded with 25pF, measured between V Note 12: Measured between V (max) and V IL Figure 13-1. Transmitter Framer Interface Timing Diagram TCLK (NORMAL) TCLK (INVERTED) t8 TPOS/TDAT, TNEG DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs (Figure 13-1 and Figure 13-2) SYMBOL CONDITIONS (Note 4) (Note 5) t1 (Note 6) ...
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... Note 13: An interfering signal ( PRBS for DS3/STS- added to the wanted signal. The combined signal is passed through 0 to 900ft of coaxial cable and presented to the DS3154 receiver. This spec indicates the lowest signal-to-noise ratio that results in a bit error ratio <10 Note 14: Not tested during production test. ...
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... Note 20 gapped clock is applied on TCLK and diagnostic loopback is enabled, read cycle time must be extended by the length of the largest TCLK gap. Note 21: Not tested during production test. Note 22: In nonmultiplexed bus applications should be wired to D[5:0] and the falling edge of ALE latches the address. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs PARAMETER PARAMETER ) ( Figure 13-3 ...
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... Figure 13-3. CPU Bus Timing Diagram (Nonmultiplexed) INTEL READ CYCLE A[5:0] D[7: INTEL WRITE CYCLE A[5:0] ADDRESS VALID D[7: DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs ADDRESS VALID DATA VALID t10 t10 ...
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... Figure 13-3. CPU Bus Timing Diagram (Nonmultiplexed)(continued) MOTOROLA READ CYCLE A[5:0] D[7:0] R MOTOROLA WRITE CYCLE A[5:0] D[7:0] R DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs ADDRESS VALID DATA VALID t2 t3 ADDRESS VALID t10 t10 ...
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... NOTE: TO AVOID BUS CONTENTION, STOP DRIVING A[5:0] BEFORE RD GOES LOW. INTEL WRITE CYCLE t13 ALE t11 ADDRESS A[5:0] VALID t14 D[7:0] t14 NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER OCCURS LAST. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs t12 DATA VALID t2 t3 t12 t10 ...
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... NOTE: TO AVOID BUS CONTENTION, STOP DRIVING A[5:0] BEFORE RD GOES LOW. MOTOROLA WRITE CYCLE t13 ALE t11 ADDRESS A[5:0] VALID t14 D[7:0] t14 R NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF ALE OR A VALID ADDRESS, WHICHEVER OCCURS LAST. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs t12 DATA VALID t2 t3 t12 t10 ...
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... JTCLK to JTDO Delay JTCLK to JTDO High-Z Delay (Note 24) JTRST Width Low Time Note 23: Clock can be stopped high or low. Note 24: Not tested during production test. Figure 13-5. JTAG Timing Diagram JTCLK JTDI, JTMS, JTRST t6 JTDO JTRST DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs (Figure 13-5) SYMBOL t1 t2/ ...
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... PIN ASSIGNMENTS Table 14-A lists pin assignments sorted by signal name. DS3154 has all four LIUs. DS3153 has only LIUs 1, 2, and 3. DS3152 has only LIUs 1 and 2. DS3151 has only LIU 1. Figure 14-1 through Figure 14-8 Table 14-A. Pin Assignments Sorted by Signal Name ...
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... RXPn Y STMCLK Y STSn Y T3MCLK Y TBIN Y TCINV Y TCLKn Y TDMn Y TDSAn Y TDSBn Y TEST Y TJAn Y TLBOn Y TNEGn Y TPOSn Y TTSn Y TXNn Y TXPn DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs CPU LIU 1 LIU K10 Y C2 K11 L11 Y A2 M11 Y A3 M10 G11 H12 Y D3 J10 N G2 F11 N G3 F10 ...
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... TTS1 E2 E3 TLBO1 D0 E4 JTCLK JTCLK DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs DS3153 HARDWARE CPU BUS HARDWARE MODE MODE MODE RLOS1 RLOS1 RLOS1 RXN1 RXN1 RXN1 RXP1 RXP1 RXP1 RMON1 N.C. RMON1 T3MCLK T3MCLK T3MCLK TXN3 TXN3 N.C. TXP3 TXP3 N.C. TCLK3 TCLK3 N ...
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... RXP4 K2 N.C. N.C. K3 RNEG4 RNEG4 TDM4 TDM4 K4 K5 TLBO4 N.C. K6 E3M4 A0 K7 TDSB4 A2 K8 RLB2 A4 DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs DS3153 HARDWARE CPU BUS HARDWARE MODE MODE MODE RLB3 N.C. N.C. LLB3 N.C. N.C. E3MCLK E3MCLK E3MCLK TXP1 TXP1 TXP1 STS1 D1 STS1 ...
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... TXP4 TXP4 M7 TXN4 TXN4 M8 STMCLK STMCLK M9 RMON2 N.C. M10 RXP2 RXP2 M11 RXN2 RXN2 RLOS2 RLOS2 M12 DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs DS3153 HARDWARE CPU BUS HARDWARE MODE MODE MODE TJA2 N.C. TJA2 RNEG2 RNEG2 RNEG2 RPOS2 RPOS2 RPOS2 RCLK2 RCLK2 RCLK2 N ...
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... TXP1 STS1 E3M1 TXN1 TDSA1 TDSB1 RST N.C. N.C. JTDI N.C. N.C. N.C. JTDO N.C. N.C. N.C. N. N.C. N.C. N.C. N. N.C. N.C. N.C. N.C. High-Speed Analog High-Speed Digital Low-Speed Digital DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs T3MCLK N.C. N. LLB1 N.C. N. RLB1 N.C. N. JTMS ...
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... JTRST TPOS1 TNEG1 TTS1 TCLK1 D0 JTCLK TXP1 TXN1 RST D5 D6 JTDI N.C. N.C. D7 JTDO N.C. N.C. N.C. N. N.C. N.C. N.C. N. N.C. N.C. N.C. N.C. High-Speed Analog High-Speed Digital Low-Speed Digital DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs T3MCLK N.C. N. INT MOT ALE JTMS TEST ...
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... TXP1 STS1 E3M1 TXN1 TDSA1 TDSB1 RST N.C. N.C. JTDI N.C. N.C. N.C. JTDO N.C. N.C. N.C. N. N.C. N.C. N.C. N. N.C. N.C. N.C. N.C. High-Speed Analog High-Speed Digital Low-Speed Digital DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs T3MCLK N.C. N. LLB1 N.C. N. RLB1 N.C. N. JTMS ...
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... TDM1 JTRST TPOS1 TNEG1 TTS1 TCLK1 D0 JTCLK TXP1 TXN1 RST D5 D6 JTDI N.C. N.C. D7 JTDO N.C. N.C. N.C. N. N.C. N.C. N.C. N. N.C. N.C. N.C. N.C. High-Speed Analog High-Speed Digital Low-Speed Digital DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs T3MCLK N.C. N. INT MOT ALE JTMS ...
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... TXN1 TDSA1 TDSB1 RST N.C. N.C. JTDI N.C. N.C. N.C. JTDO N.C. N.C. N.C. N. N.C. N.C. N.C. N. N.C. N.C. N.C. N.C. High-Speed Analog High-Speed Digital Low-Speed Digital DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs T3MCLK TXN3 TXP3 LLB1 TDSA3 STS3 RLB1 TDSB3 E3M3 JTMS ...
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... TPOS1 TNEG1 TTS1 TCLK1 D0 JTCLK TXP1 TXN1 RST D5 D6 JTDI N.C. N.C. D7 JTDO N.C. N.C. N.C. N. N.C. N.C. N.C. N. N.C. N.C. N.C. N.C. High-Speed Analog High-Speed Digital Low-Speed Digital DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs T3MCLK TXN3 TXP3 INT MOT ALE JTMS TEST ...
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... Figure 14-7. DS3154 Hardware Mode Pin Assignment RLOS1 RXN1 RXP1 RMON1 RTS1 PRBS1 N.C. RJA1 RCLK1 RPOS1 RNEG1 TJA1 TDM1 JTRST TPOS1 TNEG1 TTS1 TCLK1 TLBO1 JTCLK TXP1 STS1 E3M1 TXN1 TDSA1 TDSB1 RST LLB4 RLB4 JTDI RMON4 RJA4 TJA4 JTDO ...
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... Figure 14-8. DS3154 CPU Bus Mode Pin Assignment RLOS1 RXN1 RXP1 N. RTS1 PRBS1 N.C. N. RCLK1 RPOS1 RNEG1 N. TDM1 JTRST TPOS1 TNEG1 TTS1 TCLK1 D0 JTCLK TXP1 TXN1 RST D5 D6 JTDI N.C. N.C. D7 JTDO TDM4 RXP4 N.C. RNEG4 RTS4 RXN4 RPOS4 TNEG4 M1 M2 ...
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... PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo.) Note: All dimensions in millimeters 1.00 (1.00) (1.00) BOTTOM VIEW DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs A1 BALL PAD CORNER 13. 1. 13. ...
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... JEDEC standard test board JA with no airflow and dissipating maximum power. Table 16-B. Theta-JA (θ ) vs. Airflow JA FORCED AIR (m/s) THETA-JA (θ 0 22.4°C/W 1 19.0°C/W 2.5 17.2°C/W DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs MIN -40 - TYP MAX UNITS °C +85 °C +125 ° ...
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... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs DESCRIPTION : -10μA min changed to -50μA min. ...