CS61577-IL1R Cirrus Logic Inc, CS61577-IL1R Datasheet
CS61577-IL1R
Specifications of CS61577-IL1R
Related parts for CS61577-IL1R
CS61577-IL1R Summary of contents
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... P. O. Box 17847, Austin, Texas, 78760 (512) 445-7222 FAX:(512) 445-7581 T1/E1 Line Interface The CS61577 is a drop-in replacement for the CS61574, and combines the complete analog transmit and receive line interface for applications in a low power, 28-pin device operating from a +5V supply. ...
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DC Supply (referenced to RGND=TGND=0V) Input Voltage, Any Pin Input Current, Any Pin Ambient Operating Temperature Storage Temperature WARNING:Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. ...
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AMI Output Pulse Amplitudes E1, 75 Ω E1, 120 Ω T1, (FCC Part 68) T1, DSX-1 Load Presented To Transmitter Output Jitter Added During Remote Loopback 10Hz - 8kHz 8kHz - 40kHz 10Hz - 40kHz Broad Band Power in 2kHz ...
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RTIP/RRING Input Impedance Sensitivity Below DSX (0dB = 2.4V) Loss of Signal Threshold Data Decision Threshold T1, DSX-1 T1, DSX-1 T1, (FCC Part 68) and E1 (Note 22) Allowable Consecutive Zeros before LOS Receiver Input Jitter Tolerance 10kHz - 100kHz ...
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GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Crystal Frequency TCLK Frequency ACLKI Frequency RCLK Duty Cycle Rise Time, All Digital Outputs Fall Time, All Digital Outputs TPOS/TNEG (TDATA) to ...
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Inputs: Logic 0 = 0V, Logic 1 = RV+) SDI to SCLK Setup Time SCLK to SDI Hold Time SCLK Low Time SCLK High Time SCLK Rise and Fall Time CS to SCLK Setup Time SCLK to CS Hold Time ...
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TPOS/TNEG Figure 3. Transmit Clock and Data Switching Characteristics SCLK t cdh t dc SDI LSB CONTROL BYTE Figure 4. Serial Port Write Timing Diagram CS SCLK t cdv SDO CLKE = 1 ...
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... THEORY OF OPERATION CS61577 Enhancements Relative to CS61574 Existing designs using the CS61574 can be con- verted to the higher performance, pin-compatible CS61577 with no changes to the PCB, external component or system software. The CS61577 provides higher performance and more features than the CS61574 including: • Selection of 75 Ω or 120 Ω E1 output op- tions under software or hardware control, • ...
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TAOS TPOS TNEG CS62180B FRAMER CIRCUIT RPOS JITTER RNEG ATTENUATOR TCODE RCODE TAOS TDATA AMI B8ZS, REPEATER HDB3, OR CODER MUX AIS RDATA DETECT BPV AIS μP SERIAL PORT 5 CONTROL CONTROL TPOS TNEG CS62180B FRAMER CIRCUIT ...
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... E1 output options. The pulse width will meet the G.703 pulse shape template shown in Figure 9, and specified in Table 4. The CS61577 will detect a static TCLK, and will force TTIP and TRING low to prevent transmis- sion when data is not present. When any transmit ...
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Percent of nominal peak 269 ns voltage 120 110 244 ns 100 194 -10 -20 219 ns 488 ns Figure 9. Mask of the Pulse at the 2048 kbps Interface Transmit All Ones Select ...
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RTIP RRING put from the phase selector feeds the clock and data recovery circuits which generate the recov- ered clock and sample the incoming signal at appropriate intervals to recover the data. Data sampling will continue at ...
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MODE CLKE (pin 5) (pin 28) DATA CLOCK LOW RPOS RCLK X (<0.2V) RNEG RCLK RPOS RCLK HIGH LOW RNEG RCLK (>(V+) - 0.2V) SDO SCLK RPOS RCLK HIGH HIGH RNEG RCLK (>(V+) - 0.2V) SDO SCLK MIDDLE X RDATA ...
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... During this activity, data will never be lost. The 32-bit FIFO in the CS61577 attenuator al- lows it to absorb jitter with minimum data delay in T1 and E1 switching or transmission applica- tions. Like the CS61574, the CS61577 will tolerate large amplitude jitter (> ...
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... Whenever more than one line interface IC resides AMI Decoder on the same circuit board, the effectiveness of the driver performance monitor can be maximized by having each IC monitor performance of a neigh- boring IC, rather than having it monitor its own performance. Note that a CS61577 can not be used to monitor a CS61574 due to output stage differences. ...
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... Bits 0 and 1 are used to clear an interrupt issued from the INT pin, which occurs in response to a loss of signal or a problem with the output driver. LSB: first bit in MSB: last bit in 7 NOTE: Setting 5, 6, & 101 or 111 puts the CS61577 into a factory test mode ...
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Writing a "1" to either "Clear LOS" or "Clear DPM" over the serial interface has three effects: 1) The current interrupt on the serial interface will be cleared. (Note that simply reading the register bits will not clear the inter- ...
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In either mode, a reset will set all reg- isters to 0 and force the oscillator to its center frequency before initiating calibration. A reset will also set LOS high. Power Supply The device operates from a single ...
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SCR ONS top 22 8 view ...
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Power Supplies RGND - Ground, Pin 22. Power supply ground for all subcircuits except the transmit driver; typically 0 Volts. RV+ - Power Supply, Pin 21. Power supply for all subcircuits except the transmit driver; typically +5 Volts. TGND - ...
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LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended Hardware Modes) Determines the shape and amplitude of the transmitted pulse to accommodate several cable types and lengths. See Table 3 for information on line ...
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TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes) Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined by TCLK. In the Host Mode, simultaneous selection of RLOOP & ...
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TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16. The AMI signal is driven to the line through these pins. The transmitter output is designed to drive a 25 Ω load between TTIP and TRING. A transformer is ...
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D2/E2 4.20 4.45 4.57 0.165 0.175 0.180 2.29 2.79 3.04 0.090 0.110 0.120 0.33 0.41 0.53 0.013 0.016 0.021 12.32 12.45 12.57 0.485 0.490 0.495 11.43 11.51 11.58 0.450 0.453 0.456 9.91 ...
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APPLICATIONS + 28 1 Control & 12 Monitor 11 RV Frame 8 Format Encoder/ 3 Decoder XTL 10 Frequency MHz 6.176 MHz 1.544 (T1) 8.192 MHz 2.048 (E1) Line Interface Figures A1-A3 show typical ...
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RGND 21 RV+ 28 TAOS 1 ACLKI 26 Control RLOOP & 27 LLOOP Monitor 12 LOS 11 DPM 5 MODE 7 RPOS 6 RNEG Frame 8 RCLK Format Encoder/ 3 TPOS Decoder 4 TNEG ...
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... Transmit Side Jitter Attenuation In some applications it is desirable to attenuate jitter from the signal to be transmitted. A CS61577 in local loopback mode can be used as a jitter attenuator. The inputs to the jitter attenuator are TPOS, TNEG, TCLK. The outputs from the jitter attenuator are RPOS, RNEG and RCLK. ...
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... Min (Note 1) = 11.6 pF (Note 2) 8.192410 8.191795 = 19.0 pF (Note 3) = 37.0 pF (Note 2) Typ Max - 370 390 - - 6.176000 6.176154 - - 6.175197 Typ Max - 210 245 - - 8.192000 8.192205 - - 8.191590 CS61577 Units ppm MHz MHz MHz Units ppm MHz MHz MHz DS155F2 ...
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... REVISION HISTORY Revision Date F Jul ’09 DS155F2 Changes Removed development system info. (No longer supported). Removed PDIP option. Changed PLCC package option to lead-free. CS61577 29 ...
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... ING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 30 CS61577 DS155F2 ...