Si3227-C-GQ Silicon Laboratories Inc, Si3227-C-GQ Datasheet - Page 12

Telecom Line Management ICs Dual Chanel Wideband SLIC/CODEC

Si3227-C-GQ

Manufacturer Part Number
Si3227-C-GQ
Description
Telecom Line Management ICs Dual Chanel Wideband SLIC/CODEC
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of Si3227-C-GQ

Product
Telecom
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Si3208/9
12
Table 11. Switching Characteristics—PCM Highway Interface
(V
PCLK Period
Valid PCLK Inputs
FSYNC Period
PCLK Duty Cycle Tolerance
FSYNC Jitter Tolerance
Rise Time, PCLK
Fall Time, PCLK
Delay Time, PCLK Rise to DTX Active
Delay Time, PCLK Rise to DTX
Transition
Delay Time, PCLK Rise to DTX
Tristate
Setup Time, FSYNC to PCLK Fall
Hold Time, FSYNC to PCLK Fall
Setup Time, DRX to PCLK Fall
Hold Time, DRX to PCLK Fall
FSYNC Pulse Width
Notes:
DD
1. All timing is referenced to the 50% level of the waveform. Input test levels are V
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Spec applies to PCLK fall to DTX tristate when that mode is selected.
= 3.13 to 5.25 V, T
3
Parameter
2
A
= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, C
Symbol
t
t
t
t
t
jitter
t
t
t
t
t
su1
su2
t
wfs
t
dty
d1
d2
d3
h1
h2
t
t
Preliminary Rev. 0.33
fs
p
r
f
Conditions
Test
L
Min
= 20 pF)
122
40
25
20
25
20
t
p
1
IH
– V
I/O
1.024
1.536
1.544
2.048
4.096
8.192
Typ
512
768
125
50
– 0.4 V, V
1
125 µs–t
IL
Max
3906
±120
= 0.4 V.
60
25
25
20
20
20
1
p
Units
MHz
MHz
MHz
MHz
MHz
MHz
kHz
kHz
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%

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