NJW#1197FC2 NJR, NJW#1197FC2 Datasheet - Page 8

• Manufacturer Part Number: NJW#1197FC2
• Description: Video ICs 8CH ELECT VOLUME
• Manufacturer: NJR

Specifications of NJW#1197FC2

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NJW1197A
NJW1197A control data is constructed with 16bits.
MSB
MSB
* Chip address is set by chip address select terminal (ADR) status.
* The mute function can be controlled externally. If the Mute control terminal (71pin) is switched to High,
Multi-Channel outputs are muted immediately (hardware mute).
– 8 –
TC/B
BC/B
D15
D15
LS,RSch Volume Output
External mute control terminal
CONTROL DATA
SWch Volume Output
L,Rch Volume Output
terminal (ADR : 17pin)
Selector
chip address select
L,Rch
Input Selector
Gain Control
Gain Control
Gain Control
Gain Control
(MUTE: 71pin)
REC B Selector
D14
D14
High
High
Low
Low
Tone Control Treble
Input Signal A
Multi channel
Tone Control Bass
D13
SW channel Volume Control
D13
RS channel Volume Control
RB channel Volume Control
LS channel Volume Control
LB channel Volume Control
R channel Volume Control
C channel Volume Control
L channel Volume Control
Selector
Cch
Differential
D12
Output
D12
REC
LB,RBch Volume Output
B1
Cch Volume Output
Data
Input Selector
Gain Control
Gain Control
Gain Control
D11
Input Selector
REC
D11
D3
A4
0
0
Input Signal C
Multi Channel
LS,RSch
Selector
Mute cancellation
Chip Address
REC A Selector
D2
TSW
D10
Don’t
D10
Care
REC
1
1
Setting
A3
Mute
Input Signal B
Multi Channel
REC A
D1
0
0
PRELIMINARY
BSW
D9
Don’t
Care
Don’t
Care
REC
D9
A2
LB,RBch
Selector
Selector
REC B
SWch
D0
0
1
SWch
RECSW
RBch
LSch
RSch
LBch
Cch
Lch
Rch
SSW
D8
Don’t
Don’t
Don’t
Care
Care
REC
Care
D8
A1
Volume Control 2
Volume Control 7
Volume Control 8
Volume Control 1
Volume Control 3
Volume Control 4
Volume Control 5
Volume Control 6
D7
D7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Select Address
D6
SWch
LSch
RBch
RSch
D6
Rch
Cch
LBch
Lch
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D5
D5
Tone Control
Tone Control
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BSW
D4
D4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SSW
D3
D3
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
TSW
TSW
Chip Address
D2
D2
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
D1
D1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
LSB
LSB
D0
D0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*