TDA8754HL14BE-S NXP Semiconductors, TDA8754HL14BE-S Datasheet - Page 36
![Video ICs TRPL 8BIT VIDEO ADC](/photos/27/77/277798/qfp144_sml.jpg)
TDA8754HL14BE-S
Manufacturer Part Number
TDA8754HL14BE-S
Description
Video ICs TRPL 8BIT VIDEO ADC
Manufacturer
NXP Semiconductors
Datasheet
1.TDA8754HL11C155.pdf
(57 pages)
Specifications of TDA8754HL14BE-S
Operating Supply Voltage
3 V to 3.6 V
Supply Current
180 mA
Maximum Operating Temperature
+ 70 C
Package / Case
SOT-486
Available Set Gain
6 dB
Bandwidth
700 MHz
Conversion Rate
140 msps
Maximum Power Dissipation
1.3 W
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Channels
3
Resolution
8 bit
Snr
48 dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
TDA8754HL/14/C1,55
Philips Semiconductors
Table 56:
Table 57:
Table 58:
9397 750 14984
Product data sheet
Bit
5
4
3
2
1
0
Bit
7 to 5
4
3
2
Bit
Symbol
Reset
Access
OUTPUTEN2 - output enable 2 register (address 19h) bit description
CLKOUTPUT - clock output register (address 1Ah) bit allocation
CLKOUTPUT - clock output register (address 1Ah) bit description
Symbol
DEOENRGB
HSOENRGB
HPDOEN
VSOENRGB
CLPOEN
FIELDOEN
Symbol
-
CKSELRGB
DLYCLKRGB
CKDATINV
9.19 Clock output register
X
E
7
-
W
X
6
-
Description
enables the output DEO to be set to high-impedance
enables the output HSYNCO to be set to high-impedance
enables the output HPDO to be set to high-impedance
enables the output VSYNCO to be set to high-impedance
enables the output CLPO to be set to high-impedance
enables the output FIELDO to be set to high-impedance
Description
not used
enables the selection of the signal on the pin CKDATA
enables a delay of 2 ns to be added to the clock Ckdata
enables the polarity of the output CKDATA to be inverted
0 = active signal
1 = high-impedance
0 = active signal
1 = high-impedance
0 = active signal
1 = high-impedance
0 = active signal
1 = high-impedance
0 = active signal
1 = high-impedance
0 = active signal
1 = high-impedance
0 = clock of output buffers; signal Ckdata
1 = pixel clock of the converter; signal Ckadco
0 = no delay
1 = 2 ns delay
0 = non-inverted
1 = inverted
W
X
5
-
Rev. 06 — 16 June 2005
CKSELRGB DLYCLKRGB
W
4
0
W
3
0
Triple 8-bit video ADC up to 270 Msps
CKDATINV
…continued
W
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
OUTOSCILL CKOENRGB
W
1
0
TDA8754
W
0
1
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