MT88E45BS1 Zarlink, MT88E45BS1 Datasheet - Page 3

• Manufacturer Part Number: MT88E45BS1
• Description: Caller ID CMOS 3.58MHz 3.3V 20-Pin SOIC Tube
• Manufacturer: Zarlink

Specifications of MT88E45BS1

• Package: 20SOIC
• Telecommunication Standards Supported: ANSI/TIA/EIA-716|ETSI/ETS 300 778-1|GR-30|SIN227|SIN242|SR-TSV-002476|TIA/EIA-777
• Fabrication Technology: CMOS
• Maximum Data Rate: 1212 Bd
• Typical Operating Supply Voltage: 3.3 V
• Typical Supply Current: 2.8 mA
• Minimum Operating Temperature: -40 °C
• Maximum Operating Temperature: 85 °C
• Operating Frequency: 3.58 MHz

MT88E45
Pin Description
2
Pin # Name
1
2
3
4
5
6
7
8
9
OSC1 Oscillator (Input). Crystal connection. This pin can also be driven directly from an external clock
OSC2 Oscillator (Output). Crystal connection. When OSC1 is driven by an external clock, this pin
DCLK 3-wire FSK Interface Data Clock (Schmitt Input/CMOS Output). In mode 0 (when the CB0 pin
IN1+
GS1
V
IN1-
CB0
Vss
REF
Voltage Reference (Output). Nominally Vdd/2. It is used to bias the Tip/Ring and Hybrid input op-
amps.
Tip/Ring Op-amp Non-inverting (Input).
Tip/Ring Op-amp Inverting (Input).
Tip/Ring Gain Select (Output). This is the output of the Tip/Ring connection op-amp. The op-
amp should be used to connect the MT88E45 to Tip and Ring. The Tip/Ring signal can be
amplified or attenuated at GS1 via selection of the feedback resistor between GS1 and IN1-. FSK
demodulation (which is always on Tip/Ring) or CAS detection (for MEI or BT on-hook CLIP) of the
GS1 signal is enabled via the CB1 and CB2 pins. See Tables 1 and 2.
Power supply ground.
source.
should be left open.
Control Bit 0 (CMOS Input). This pin is used primarily to select the 3-wire FSK data interface
mode. When it is low, interface mode 0 is selected where the FSK bit stream is output directly.
When it is high, interface mode 1 is selected where the FSK byte is stored in a 1 byte buffer which
can be read serially by the application’s microcontroller.
The FSK interface is consisted of the DATA, DCLK and DR/STD pins. See the 3 pin descriptions
to understand how CB0 affects the FSK interface.
When CB0 is high and CB1, CB2 are both low the MT88E45 is put into a power down state
consuming minimal power supply current. See Tables 1 and 2.
is logic low) this is a CMOS output which denotes the nominal mid-point of a FSK data bit.
In mode 1 (when the CB0 pin is logic high) this is a Schmitt trigger input used to shift the FSK data
byte out to the DATA pin.
OSC1
OSC2
DCLK
DATA
V
IN1+
CB0
GS1
IN1-
Vss
REF
Figure 2 - Pin Connections
1
2
3
4
5
6
7
8
9
10
MT88E45
Description
20
19
18
17
16
15
14
13
12
11
CB1
Vdd
CD
ST/GT
EST
DR/STD
IN2+
IN2-
GS2
CB2
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