MT88E46AS Zarlink, MT88E46AS Datasheet - Page 2
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MT88E46AS
Manufacturer Part Number
MT88E46AS
Description
Caller ID CMOS 3.58MHz 3.3V/5V 20-Pin SOIC Tube
Manufacturer
Zarlink
Datasheet
1.MT88E46ASR1.pdf
(23 pages)
Specifications of MT88E46AS
Package
20SOIC
Telecommunication Standards Supported
Bellcore GR-30-CORE|SR-TSV-002476|TIA/EIA-716|TIA/EIA-777
Fabrication Technology
CMOS
Maximum Data Rate
1.212 KBd
Typical Operating Supply Voltage
3.3|5 V
Typical Supply Current
4.3 mA
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
85 °C
Operating Frequency
3.58 MHz
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT88E46AS
Manufacturer:
MITEL
Quantity:
20 000
Company:
Part Number:
MT88E46AS1
Manufacturer:
ZARLINK
Quantity:
595
Pin Description
MT88E46
Change Summary
Changes from March 2000 Issue to November 2006 Issue.
2
Pin #
Page
1
1
2
3
4
5
6
7
8
Item
Name
OSC1
OSC2
IN1+
V
IN1-
GS1
CB0
Vss
REF
Voltage Reference (Output). Nominally Vdd/2. It is used to bias the GS1 (Tip/Ring connection) and
GS2 (telephone hybrid or speech IC receive pair connection) input op-amps.
GS1 Op-Amp Non-inverting Input. The op-amp is for connecting the MT88E46 to Tip/Ring.
GS1 Op-Amp Inverting Input. The op-amp is for connecting the MT88E46 to Tip/Ring.
Gain Select 1 (Output). This is the output of the GS1 op-amp. The op-amp should be used to connect the
MT88E46 to Tip and Ring. The Tip/Ring signal can be amplified or attenuated at GS1 via selection of the
feedback resistor between GS1 and IN1-.
FSK demodulation or ‘on hook mode’ CAS detection of the GS1 signal can be selected via the CB1 and
CB2 pins. See Tables 1 and 2.
Power Supply Ground.
Oscillator Input. Crystal connection. This pin can also be driven directly from an external clock source.
Oscillator Output. Crystal connection. When OSC1 is driven by an external clock, this pin should be left
open circuit.
Control Bit 0 (CMOS Logic Input). This pin is used primarily to select the 3-wire FSK data interface
mode. When it is low, interface mode 0 is selected where the FSK bit stream is output directly at the
DATA pin. When it is high, interface mode 1 is selected where the FSK byte is stored in a 1 byte buffer
which can be read serially by the application’s microcontroller.
The FSK interface is consisted of the DATA, DCLK and DR/DET pins. See the 3 pin descriptions to
understand how CB0 affects the FSK interface.
This pin is also used with CB1 and CB2 to put the MT88E46 into a power down state drawing virtually
no power supply current. See Tables 1 and 2.
OSC1
OSC2
DCLK
DATA
V
IN1+
CB0
GS1
IN1-
Vss
REF
Figure 2 - Pin Connections
1
2
3
4
5
6
7
8
9
10
Change
Updated Ordering Information.
MT88E46
Description
20
19
18
17
16
15
14
13
12
11
CB1
Vdd
CD
NC
IC
DR/DET
IN2+
IN2-
GS2
CB2
Data Sheet