LE57D122BTC Zarlink, LE57D122BTC Datasheet

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LE57D122BTC

Manufacturer Part Number
LE57D122BTC
Description
SLIC 2-CH 67dB 120mA 5V 44-Pin LQFP EP Tray
Manufacturer
Zarlink
Datasheet

Specifications of LE57D122BTC

Package
44LQFP EP
Number Of Channels Per Chip
2
Polarity Reversal
Yes
Longitudinal Balanced
67 dB
Loop Current
120 mA
Minimum Operating Supply Voltage
4.75 V
Typical Operating Supply Voltage
5 V
Typical Supply Current
9.3 mA

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LE57D122BTC
Manufacturer:
ZARLINK
Quantity:
950
Part Number:
LE57D122BTC
Manufacturer:
LEGERITY
Quantity:
852
Part Number:
LE57D122BTCT
Manufacturer:
ZARLINK
Quantity:
950
APPLICATIONS
FEATURES
ORDERING INFORMATION
1.
2.
Le57D121BTC
Le57D122BTC
Ideal for low-cost, high performance line card
applications (CO, DLC)
Meets requirements for countries such as: India,
China, Korea, Japan, Taiwan, and Australia
Meets requirements for North America DLC
applications (TR-57-CORE)
Dual-Channel SLIC device with small footprint
Loop start and Ground start support
+5 V and battery supply required
Optional dual battery operation
–39 to –60 V battery operation
Supplies more than 20 mA into 2000 Ω from –48 V
Programmable current limit
On-chip Thermal Management (TMG) feature in all
Active states
Low standby power (24 mW per channel)
Supports 2.0 Vrms metering applications
Control states: Active and Active Metering (Normal and
Reverse Polarity), Standby, Tip Open and Disconnect
3.3-V compatible to logic control inputs
Power up in Disconnect state
On-hook transmission in Active states
Per-channel fault detection and indication
Per-channel thermal shutdown
Programmable Off Hook and Ground Start thresholds.
Programmable ring-trip detect threshold
Footprint compatible with Zarlink’s Le5711 Dual SLIC
The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
For delivery using a tape and reel packing system, add a "T" suffix
to the OPN (Ordering Part Number) when placing an order.
Device
44-pin eTQFP (Green),
–53 dB, Reverse Polarity
44-pin eTQFP (Green),
–63 dB, Reverse Polarity
Package Type
1
Tray
Packing
2
Dual Subscriber Line Interface Circuit
DESCRIPTION
The innovative Le5712 dual-channel SLIC device is designed
for high-density POTS applications requiring a small-footprint,
low-power SLIC device. By combining a fully featured line
interface of two channels into one SLIC device, the Le5712
device enables the design of a low-cost, high performance, and
fully programmable line interface for multiple country
applications worldwide, including Ground Start and metering
capability. The on-chip Thermal Management (TMG) feature
allows for significantly reduced power dissipation on the
device. Optional dual battery operation to reduce total power
consumption is also available. The device is offered in a
thermally efficient, space-saving 44-pin eTQFP package. The
12 x 12 mm footprint allows designers to make a dramatic
increase in the density of lines on a board. The Le5712 device
is also designed to significantly reduce the number of external
components required for line card design.
Zarlink offers a range of compatible SLAC™ devices that
perform the codec function in a line card. In particular, the
Zarlink Quad and Octal SLAC devices combined with the
Le5712 device provides a programmable line circuit that can
be configured for varying requirements.
RELATED LITERATURE
BLOCK DIAGRAM
BGND
TMG
RSN
VTX
AD
HP
BD
081110 Thermal Management for the Le5711 and
Le5712 SLIC Devices Application Note
080900 Le5711 and Le5712 Comparison Brief
Application Note
080753 Le58QL02/021/031 QLSLAC
080754 Le58QL061/063 QLSLAC
080921 Le58083 Octal SLAC
080676 Le5711 Dual SLIC Data Sheet
2
2
2
2
2
2
2
Detector
CH2
Fault
CH2
Interface
CH2
2-W
CH2
and Control
Decoder
Input
CH2
CH2
Document ID# 081047
Rev:
Distribution:
CH2
Common
Bias
CH1
G
Public Document
Data Sheet
and Control
CH1
Decoder
VE580 Series
Input
CH1
Data Sheet
Le5712
Date:
Version:
Data Sheet
CH1
Interface
CH1
2-W
Detector
Sep 18, 2007
Fault
CH1
CH1
2
120402
BGND
TMG
AD
HP
BD
VTX
RSN
1
1
1
1
1
1
1

Related parts for LE57D122BTC

LE57D122BTC Summary of contents

Page 1

... Device Package Type 44-pin eTQFP (Green), Le57D121BTC –53 dB, Reverse Polarity 44-pin eTQFP (Green), Le57D122BTC –63 dB, Reverse Polarity 1. The green package meets RoHS Directive 2002/95/EC of the European Council to minimize the environmental impact of electrical equipment. 2. For delivery using a tape and reel packing system, add a "T" suffix to the OPN (Ordering Part Number) when placing an order ...

Page 2

... Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 POTS Application Circuit (POTS with no metering .18 Application Circuit Parts List (Pots with no metering .19 Pulse Metering Application Circuit (Pots with metering .20 Application Circuit Parts List (Pots with metering .21 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Revision .23 Revision .23 Revision .23 Revision .23 Revision .23 2 Zarlink Semiconductor Inc. ...

Page 3

... I R BAT – 5 – max LIMITmin = --------------------------------------------------------------------------------------------------------------------------- R TMGmin  -------------- - BAT BAT – 3 – –   LIMITmax ------------------------ -  max TMGmax 2 3 Zarlink Semiconductor Inc. is connected from TMG to the VBAT pin and TMGi 40Ω LMIN = - MAX Lmin F I  – 5 –  TMG  ...

Page 4

... Z T 470 I = ------------- - LIMIT R REF ) can be implemented from CAS I = STANDBY 4 Zarlink Semiconductor Inc. , and an impedance connected from VTX F to RSN , where i i Ω , and supports gain ranges of at least , is given in the TR is the impedance T , filtered by a capacitor BAT 1 = ---------------------------------------- - • 2 π • • ...

Page 5

... DAC pin, and the DET i on page 18 shows a ring trip bridge configured and components on page 20 i may pulse at twice the frequency of the induction signal Zarlink Semiconductor Inc. DET output i N/A OHD GSD OHD RTD OHD ...

Page 6

... Pin 1 is marked for orientation Connect 3. The exposed heat sink pad on the bottom of the eTQFP package should be connected to VBAT pin - the SLIC side of the diode from battery supply. Do not connect it to GND 44-Pin eTQFP Exposed Pad Zarlink Semiconductor Inc. 33 BGND DAC VBAT ...

Page 7

... Battery supply and connection to substrate. Connect to highest negative supply with a diode on a per line base. This is a Zarlink reserved pin and must always be connected to the VBAT pin power supply. Transmit audio signal of channel 1. This output is a scaled version of the A and B metallic voltage ...

Page 8

... Environmental Ranges Zarlink guarantees the performance of this device over commercial (0 to 70º C) and industrial (−40 to 85º C) temperature ranges by conducting electrical characterization, production testing, and periodic sampling over each range. These characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE Component Reliability Assurance Requirements for Telecommunications Equipment ...

Page 9

... Ω BGND AD to BAT=7 kΩ GND=100Ω 3.4 kHz V = 100 mVrms RIPPLE V = 100 mVrms RIPPLE 300 Hz to 3.4 kHz CAS pin to AGND 9 Zarlink Semiconductor Inc. Figure 7, on page 17 SLIC Device Power mW Max Min. Typ Max 10.0 353 540 10 ...

Page 10

... BXi = C = 2.2 nF BXi Figure 16) –50 2.5 1.1 5.5 5.5 = 600 Ω LAC = 300 Ω = 600 Ω 600 Ω 300 Ω Zarlink Semiconductor Inc. Typ Max Unit Note -67 dB - mArms 5 Ω /pin 18.5 1 mVrms Ω ...

Page 11

... –50 –50 V BAT 8 Figure 1, on page 15.) 9.8 1.3 11.8 2.6 11 Zarlink Semiconductor Inc. Typ Max Unit Note 0 +0.20 –9.54 –9.34 –9.54 –9.34 +0.35 dB +0.15 +0.15 2 +0.15 +0.35 15.6 16 0.8 90 µA 0. ...

Page 12

... Vrms source. The typical gain is 15.6 dB. 13. Tested with 0 Ω source impedance. 2 MΩ is specified for system design only. network such as that shown in Figure 5, on page Ω. The output voltage at tip/ring is expected Vrms, into a load of 300 Ω Zarlink Semiconductor Inc. where C = 120 pF ...

Page 13

... TMGmax TMGmax 13 Zarlink Semiconductor Inc. Description connected between the VTX and Ti RSN pins. The fuse resistors are the desired 2-wire AC input 2WIN impedance. When computing Z internal current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account ...

Page 14

... R = ------------- -R AB1 LOOP L R REF BAT – + AB2 BAT – + AB3 V = BAT – 10.7 V AB2 V = BAT – 10.7 V AB3 14 Zarlink Semiconductor Inc. V AB2 V AB1 071902 , , where ⋅ ⋅ 47 kΩ V ⋅ 160 Ω -------------------------- - I – REF ⋅ ⋅ 10 kΩ V ⋅ 160 Ω ...

Page 15

... Figure 3. Four-to-Two Wire Insertion Loss and Balance Return Signals Figure 1. Feed Programming IREF i RD DSLIC DET CDC i Figure 2. Two-to-Four Wire Insertion Loss VTX VTX 2 DSLIC AGND RSN RSN log L2 VTX VTX 2 DSLIC V TX AGND RSN RSN log L4 BRS = 20 log Zarlink Semiconductor Inc. R REF ...

Page 16

... L DSLIC AGND L RSN RSN 2 S2 Closed, S1Open ) 4-L Long. Sig. Gen log VTX VTX DSLIC V M AGND = 600 Ω RSN RSN Figure 6. RFI Test Circuit C 200 Ω Ω RF 200 Ω Ω Zarlink Semiconductor Inc VTX BD 1 VTX 2 DSLIC under test ...

Page 17

... VCC AGND RSN /DGND Le5712x VTX 1 CDC 1 CH1 FLT 1 DET IREF RD RSN 2 VTX 2 CDC 2 CH2 FLT 2 DET Zarlink Semiconductor Inc. 16 150 k VRX 1 R RX1 R T1 100 k VTX 1 C DC1 330 nF FLT 1 DET REF D 16 150 k VRX 2 R RX2 R T2 100 k VTX 2 C ...

Page 18

... HP1 CDC R CH1 HP1 BD1 R TMG1 TMG 1 VBAT R TMG2 TMG 2 VBREF CAS C CAS DB RSN 1 DAC DB 2 CDC AD CH2 HP2 R HP2 BD2 ANALOG GROUND 18 Zarlink Semiconductor Inc. DAC VOUT RX1 VRX1 VTX1 VTX VIN TX1 1 C DC1 DET CD1 1 1 FLT CD2 ...

Page 19

... Capacitor (X7R) 0.022 µF Capacitor (X7R) 0.1 µF Capacitor (X7R) 0.01 µF Capacitor (X7R) 0.1 µF Capacitor (X7R) 0.33 µF Capacitor (X7R) 0.33 µF SMT 2.00 kΩ Le5712x is greater than 0.01µF. 19 Zarlink Semiconductor Inc. Tol. Rating Note 20% ...

Page 20

... Le5712x HP1 CH1 R HP1 BD1 R TMG1 TMG 1 VBAT R TMG2 TMG 2 VBREF CAS C CAS DB 1 DAC DB 2 AD2 AD CH2 HP2 R HP2 BD2 ANALOG GROUND 20 Zarlink Semiconductor Inc. DAC RSN VOUT RX1 VRX1 TA1 TB1 VTX1 VTX VIN 1 C CDC DC1 DET ...

Page 21

... Capacitor (X7R) 0.022 µF Capacitor (X7R) 0.1 µF Capacitor (X7R) 0.1 µF Capacitor (X7R) 0.1 µF Capacitor (X7R) 0.33 µF Capacitor (X7R) 0.33 µF Le5712x Ω at tip-ring (20LOG(200/16.5/1000*500/(1+500/3.0841*(200+100)/22.1/1000)). 21 Zarlink Semiconductor Inc. Tol. Rating Note 20% ...

Page 22

... BSC D2 0.08 - 0. aaa 0 deg 3.5 deg 7 deg bbb 0 deg - - ccc 11 deg 12 deg 13 deg ddd 11 deg 12 deg 13 deg N 44-Pin eTQFP 22 Zarlink Semiconductor Inc. Nom Max - 0.20 0.60 0.75 1.00 REF - - 0.20 0.27 0.80 BSC 8.00 8.00 0.20 0.20 0.10 0.20 44 ...

Page 23

... Application Circuit Parts List (Pots with metering), • Modified Revision • Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007 , Ground Start Detection Threshold, changed max from 15.2mA to 16.0mA. GSD , changed max from 18mA to 20mA. FAULT , Input High Current of C1/2/3, changed max from ...

Page 24

... Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...

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