LE79R241DJC Zarlink, LE79R241DJC Datasheet - Page 10

• Manufacturer Part Number: LE79R241DJC
• Description: SLIC 1-CH 63dB 70mA 5V 32-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of LE79R241DJC

• Package: 32PLCC
• Number Of Channels Per Chip: 1
• Polarity Reversal: Yes
• Longitudinal Balanced: 63 dB
• Loop Current: 70(Min) mA
• Minimum Operating Supply Voltage: 4.75 V
• Typical Operating Supply Voltage: 5 V
• Typical Supply Current: 7.5 mA

ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Stresses greater than those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods can affect device reliability
Note:
1.
2.
Thermal Resistance
The junction to air thermal resistance of the Le79R241 ISLIC device in a 32-pin PLCC package is 45° C/W and in a 32-pin QFN
package is 25° C/W (measured under free air convection conditions and without external heat sinking).
Package Assembly
The standard (non-green) package devices are assembled with industry-standard mold compounds, and the leads possess a tin/
lead (Sn/Pb) plating. These packages are compatible with conventional SnPb eutectic solder board assembly processes. The
peak soldering temperature should not exceed 225°C during printed circuit board assembly.
Green package devices are assembled with enhanced, environmental compatible lead-free, halogen-free, and antimony-free
materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer lead-
free board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly.
Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile.
Thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 165°C. Operation above 145°C junction
temperature may degrade device reliability.
The thermal performance of a thermally enhanced package is assured through optimized printed circuit board layout. Specified performance
requires that the exposed thermal pad be soldered to an equally sized exposed copper surface, which, in turn, conducts heat through mul-
tiple vias to a large internal copper plane.
Rise time of VBH (dv/dt) must be limited to less than 27 v/ms.
Storage temperature
Ambient temperature, under bias
Humidity
VCC with respect to GND
VBH, VBL with respect to GND (See note 2)
BGND with respect to GND
Voltage on relay outputs
AD or BD to BGND:
Current into SA or SB:
Current into SA or SB:
SA SB continuous
Current through AD or BD
P1, P2, P3, LD to GND
Maximum power dissipation (see note 1)
ESD Immunity (Human Body Model)
Continuous
10 ms (F = 0.1 Hz)
1 µs (F = 0.1 Hz)
250 ns (F = 0.1 Hz)
T
T
A
A
10 µs rise to Ipeak
1000 µs fall to 0.5 Ipeak;
2000 µs fall to I =0
2 µs rise to Ipeak
10 µs fall to 0.5 Ipeak;
20 µs fall to I = 0
= 70° C
= 85° C
In 32-pin PLCC package
In 32-pin QFN package
In 32-pin PLCC package
In 32-pin QFN package
Zarlink Semiconductor Inc.
10
–55 to +150°C
–40 to +85°C
–0.4 to +7 V
–3 to +3 V
+7 V
5 mA
1.67 W
3.00 W
1.33 W
2.40 W
JESD22 Class 1C compliant
5% to 95%
+0.4 to –104 V
VBH – 1 to BGND + 1
VBH – 5 to BGND + 5
VBH – 10 to BGND + 10
VBH – 15 to BGND + 15
Ipeak = ±5 mA
Ipeak = ±12.5 mA
± 150 mA
–0.4 to VCC + 0.4 V