LE79R79-1DJC Zarlink, LE79R79-1DJC Datasheet
LE79R79-1DJC
Specifications of LE79R79-1DJC
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LE79R79-1DJC Summary of contents
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... Le71HE0040J Evaluation Board User’s Guide 080458 Le79R100/101 v. Le79R79 Comparison Brief 080753 Le58QL02/021/031 QLSLAC™ Data Sheet Ringing Subscriber Line Interface Circuit ORDERING INFORMATION 1 Device Package Type Le79R79-1DJC 32-pin PLCC Le79R79-2DJC (Green package) Le79R79-3DJC Le79R79-1FQC 32-pin QFN (Green package) Le79R79-2FQC ...
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... Ring Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Ground-Key Detector Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Loop Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Relay Driver Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Relay Driver Schematic .12 SLIC Device Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 User-Programmable Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Ring-Trip Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Test Circuits .17 Le79R79 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Application Circuit .21 Physical Dimensions .22 32-pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 32-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Revision .24 Revision .24 Revision .24 Revision .24 Revision ...
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... Revision .25 Revision .25 Revision .25 3 Zarlink Semiconductor Inc. ...
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... Zarlink codec/filter, such as the Le58QL0xx Quad SLAC (QLSLAC™) device. The Le79R79 Ringing SLIC device is a bipolar monolithic SLIC that offers on-chip ringing. Now designers can achieve significant cost reductions at the system level for short-loop applications by integrating the ringing function on chip. Examples of such applications would be ISDN terminal adaptors, fiber-in-the-loop, radio-in-the-loop, hybrid fiber/coax and video telephony (home- side) boxes ...
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... RYE 5 6 B2EN 7 VBAT1 8 32-pin PLCC DET RYE 1 2 B2EN 3 4 32-pin QFN EXPOSED PAD Zarlink Semiconductor Inc. RTRIP1 29 RTRIP2 28 HPB 27 HPA 26 RINGIN 25 RDCR 24 VTX 23 VNEG 22 RSN 21 25 RTRIP2 24 23 HPB HPA 22 21 RINGIN RDCR 20 19 VTX VNEG 18 RSN 17 16 ...
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... VTX Output also sources the two-wire input impedance programming network. Description Enable. Logic Low enables operation from BAT1 and BAT2 6 Zarlink Semiconductor Inc. . Logic High enables operation from V BAT2 is negative for normal polarity RDC BAT1 ). For power conservation in any BAT1 regulator. EE ...
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... V 0 BAT2 V to GND BAT1 +0.4 to –80 V +0.4 to – –3 V – BAT1 – BAT1 – BAT1 – BAT1 ±150 RYE RYE to +10 V BGND to V BAT1 + 0.4 V –0 1.67 W 3.00 W θ JA 45° C/W 25° C/W JESD22 Class 1C compliant 7 Zarlink Semiconductor Inc. ...
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... OPERATING RANGES Zarlink guarantees the performance of this device over commercial (0 to 70º C) and industrial (-40 to 85ºC) temperature ranges by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE Component Reliability Assurance Requirements for Telecommunications Equipment ...
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... C ° +3 dBm to –55 dBm 0 to +70 –0.10 C ° −40 to +85 relative to 0 dBm C –0.15 ° +70 –0.10 0 dBm to –37 C ° −40 to +85 –0. dBm to 0 dBm –0.35 0 dBm, 1kHz 9 Zarlink Semiconductor Inc. Typ Max Unit Note mArms 4 Ω/pin 25 Min Typ ...
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... Min 50 to 3400 3400 3400 3400 Hz Test Conditions (See Note 1) Min V BAT1 V BAT2 V BAT1 V BAT1 = 300 Ω BAT1 BAT2 L = 300 Ω BAT1 L = 300 Ω BAT2 L 10 Zarlink Semiconductor Inc. Typ Max Unit Note I 1.085I 21 1. 110 55 100 µA 100 34 mA −5 ...
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... RRT1 Test Conditions (See Note 1) BAT1 = −75 V, Ringload = 1570 Ω 2.5 V RINGIN ) Test Conditions (See Note ground B to ground 11 Zarlink Semiconductor Inc. Min Typ Max Unit 3.0 4.5 3.2 5.5 6.2 8.0 6.5 9.0 0.1 0.2 0.1 ...
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... RYOUT1 RYE BGND = + 0.018 µ kΩ nF, R DCR2 DCR RT1 VTX = 150 k Ω 150 k Ω RSN = 300 k Ω Zarlink Semiconductor Inc. Min Typ Max Unit −20 20 − −15 15 Min Typ Max Unit +0.25 +0.4 V +0.30 +0.8 100 µA 6.6 7 RYOUT2 BGND = 600 Ω ...
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... Loop detector Reserved Loop detector Standby Loop detector Active Polarity Reversal Loop detector OHT Polarity Reversal Loop detector on-hook battery must be used. BAT1 13 Zarlink Semiconductor Inc. for typical value LTH regardless of the battery BAT1 (DET) Output Battery Ring trip Ring trip B2EN ...
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... This equation shows at what resistance the Standby threshold is 400 2R – F actually a current threshold rather than a resistance threshold, which is shown by the V BAT 14 Zarlink Semiconductor Inc defined above, and form the network connected to the RDC pin. DC ...
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... V ASH V APPH = ------------------------------------------------------------------------------ - ( ) DC1 DC2 -------------------------------------- + LOOP 600 15 Zarlink Semiconductor Inc ASH 1) Constant-Current Region 2) V ASL resistor to GND, B2EN = logic Low. SGL = resistor B2EN = logic Low. SGL CC must be greater than 100 kΩ resistor to GND, B2EN = logic High. SGH = resistor B2EN = logic High. SGH ...
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... This is the best time for switching between Ringing and other states for minimizing detect switching transients. Figure 5. Feed Programming A (TIP) RSN SLIC L B (RING) RDC Feed current programmed by R and R DC1 16 Zarlink Semiconductor Inc. • 150 + 2R LRT F Ringing Reference (Input SLEW ...
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... L-4 Long. Bal log(V Figure 6. Two-to-Four-Wire Insertion Loss A (TIP) VTX SLIC V AB AGND B (RING) RSN log L2 (TIP) VTX SLIC AGND B (RING BRS = 20 log Figure 8. Longitudinal Balance VTX A (TIP SLIC AGND (RING Closed, S1Open / V ) 4-L Long. Sig. Gen log Zarlink Semiconductor Inc ...
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... Figure 9. Two-Wire Return Loss Test Circuit The desired impedance; D eg., the characteristic impedance of the line Return loss = –20 log ( Figure 10. Loop-Detector Switching = 600 Ω Figure 11. Ground-Key Switching A (TIP) VTX R T1 SLIC AGND (RING) RSN V CC 6.2 k Ω A (TIP) DET B (RING (TIP) B (RING Zarlink Semiconductor Inc ...
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... HF GEN 50Ω 1.5 Vrms 80% Amplitude Modulated 100 kHz to 30 MHz Figure 12. RFI Test Circuit 200Ω 1 200Ω Zarlink Semiconductor Inc (TIP) 50Ω 33nF 50Ω B (RING) RF VTX 33nF SLIC under test ...
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... Le79R79 TEST CIRCUIT RT1 RT RT2 430 k Ω 1.5 µF 12 kΩ 2 (TIP (RING 2.2 nF RYOUT1 RYOUT2 RYE D 1 BAT1 0.1 µ BAT2 0.1 µF Note: 1. Refer to the Applications Circuit on the next page for recommended configuration. 2. The input should be 50% duty cycle CMOS-compatible input. ...
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... CF 5. 925 Ω LOOP 6. 600 Ω 3. 100 mA Ringing Current Limit Note: The input should be 50% duty cycle CMOS-compatible input. RTRIP1 VCC VNEG RT1 RTRIP2 U1 RSGH Le79R79 RSGL A(TIP) VTX HPA HPB RSN B(RING) RDC RDCR RYOUT1 RYOUT2 RYE B2EN VBAT1 VBAT2 ...
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... Exact shape of this feature is optional. 0.550 0.553 5 Details of pin 1 identifier are optional but must be located -- 10 deg within the zone indicated. 6 Sum of DAM bar protrusions to be 0.007 max per lead. 7 Controlling dimension : Inch. 8 Reference document : JEDEC MS-016 32-Pin PLCC 22 Zarlink Semiconductor Inc. ...
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... The Terminal #1 identifier may be either a mold or marked feature. 5.90 5. Coplanarity applies to the exposed pad as well as the terminals. 6. Reference Document: JEDEC MO-220. 0.63 7. Lead width deviates from the JEDEC MO-220 standard. 0.05 32-Pin QFN 23 Zarlink Semiconductor Inc degrees. ...
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... REVISION HISTORY Revision • Minor changes were made to the data sheet style and format to conform to Zarlink standards. • Electrical Characteristics; Last row under Ring Signal, min changed from 130 to 150, typ changed from 160 to 180, and max changed from 190 to 210. ...
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... Revision • Removed OPNs for all non-green packaged parts from • Removed 79R79-3QC, 79R79-4JC and 79R79-4QC from Revision • Removed reference to Le79R79-4 option from Revision • Changed I Loop-Current Accuracy from 0.915 to 0. Revision • Enhanced format of package drawings in • Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007 ...
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... Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...