ADQ112 Sp Devices, Inc., ADQ112 Datasheet - Page 7

• Manufacturer Part Number: ADQ112
• Description: High Speed Digitizer
• Manufacturer: Sp Devices, Inc.

Specifications of ADQ112

• Transmission Media Type: Cable
• Power Supply Type: Analog
• Typical Operating Supply Voltage: 12 V

6
6.1
The ADQ112 is available with cPCIe / PXIe inter-
face.
Figure 9: cPCIe / PXIe interface
6.2
The AFE is available with a low frequency configu-
ration. The AC coupling is tuned to get a lower cut
off frequency (–3dB) at typically 0.4 Hz. This con-
figuration maintains low noise performance of the
standard AFE.
1. It is not possible to switch between different AFEs.
Document Number
08-0132
Revision
C
cPCIe / PXIe INTERFACE
Bus width
Bus peak capacity
Sustained data rate, 4 lanes 400
PXIe card size
Order code: –PXIE
Order code: –LFAFE
Options
cPCIe / PXIe interface
Low frequency AC AFE
Date
2009-12-21
Printed
2009-12-22
8
16
1 slot 3U 4TE
1
lanes
Gbit/s
MByte/s
Contact
Signal Processing Devices Sweden AB
Teknikringen 6, SE-583 33 Linköping, SWEDEN
www.spdevices.com
6.3
The ADQ112 is available with an active buffered
DC coupled AFE. The gain compared to the AC
AFE options is 18 dB which means that full scale
analog input is 0.25 V
6.4
A Decimation IP is available for integration in
FPGA#2. Decimation IP requires FPGA upgrade
to SX50T. The Decimation IP can decimate up to
2
frequency option is ideal for low frequency noise
measurements.
The Decimation IP implements a close to ideal low
pass filter, which suppresses the wide band quan-
tization noise in digitizer. The theory of decimation
gives that each factor of 4 in decimation yields
one extra bit in resolution. The effect is an
increased dynamic range.
The Decimation IP makes the ADQ112 very flexi-
ble and a large set of measurements specifica-
tions can be met with the same device.
6.5
The ADQ Development Kit opens a user area in
FPGA#2 for custom designs. The standard config-
uration for FPGA#2 is a Xilinx Virtex 5 LX30T-1
FPGA, which is enough for many applications.
However, for demanding real time signal process-
ing applications, an FPGA upgrade to Xilinx Virtex
5 SX50T-3 is available. This gives the user access
to more than 285 DSP elements. 60% of the logic
in this FPGA is also available.
2. It is not possible to switch between different AFEs.
DECIMATION IP CONFIGURATIONS (EXAMPLES)
Decimation order
2
2
2
34
0
4
12
Order code: –DCAFE
Order code: –DEC
Order code: –SX50T
= 1
= 16
times. The Decimation IP together with the low
= 4096
Active DC coupled AFE
Decimation IP
FPGA upgrade
Sampling rate
1100 MSps
68 MSps
269 kSps
PP
.
2
ADQ112
Resolution
12 bits
14 bits
18 bits
Datasheet
7(7)