89HPES24T3G2ZCALG Integrated Device Technology (Idt), 89HPES24T3G2ZCALG Datasheet - Page 4

• Manufacturer Part Number: 89HPES24T3G2ZCALG
• Description: PCI Express Switch 324-Pin FCBGA Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 89HPES24T3G2ZCALG

• Package: 324FCBGA
• Operating Temperature: 0 to 70 °C

Pin Description
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89HPES24T3G2 Data Sheet
The following tables list the functions of the pins provided on the PES24T3G2. Some of the functions listed may be multiplexed onto the same pin.
Note: In the PES24T3G2, the two downstream ports are labeled port 2 and port 4.
1.
REFCLKM is not available in the 19mm package and frequency is set at 100MHz.
SSMBADDR[5,3:1]
MSMBADDR[4:1]
PEREFCLKP
PEREFCLKN
PE0RN[7:0]
PE2RN[7:0]
PE4RN[7:0]
PE0RP[7:0]
PE0TP[7:0]
PE0TN[7:0]
PE2RP[7:0]
PE2TP[7:0]
PE2TN[7:0]
PE4RP[7:0]
PE4TP[7:0]
PE4TN[7:0]
REFCLKM
MSMBCLK
MSMBDAT
SSMBCLK
Signal
Signal
1
1
2
Type
Type
I/O
I/O
I/O
O
O
O
I
I
I
I
I
I
I
Table 3 SMBus Interface Pins (Part 1 of 2)
Table 2 PCI Express Interface Pins
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 4.
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
This pin should be static and not change following the negation of
PERSTN.
Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
4 of 48
Name/Description
Name/Description
September 29, 2010