8543BGILF Integrated Device Technology (Idt), 8543BGILF Datasheet - Page 7

• Manufacturer Part Number: 8543BGILF
• Description: Clock Driver 2-IN LVDS 20-Pin TSSOP Tube
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 8543BGILF

• Package: 20TSSOP
• Configuration: 1 x 2:1
• Input Signal Type: CML/HCSL/LVDS/LVHSTL/LVPECL/SSTL
• Maximum Output Frequency: 650 MHz
• Operating Supply Voltage: 3.3 V

Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
IDT™ / ICS™ LVDS FANOUT BUFFER
ICS8543I
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Offset from Carrier Frequency (Hz)
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to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
12kHz to 20MHz = 0.164ps (typical)
Additive Phase Jitter @ 153.6MHz
ICS8543BGI REV. E SEPTEMBER 9, 2008