MT46V32M16P-6T IT:F Micron Technology Inc, MT46V32M16P-6T IT:F Datasheet - Page 81

• Manufacturer Part Number: MT46V32M16P-6T IT:F
• Description: DRAM Chip DDR SDRAM 512M-Bit 32Mx16 2.5V 66-Pin TSOP Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V32M16P-6T IT:F

• Density: 512 Mb
• Maximum Clock Rate: 333 MHz
• Package: 66TSOP
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 2.5 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Package / Case: 66-TSOP
• Organization: 32Mx16
• Address Bus: 15b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 195mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 46:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
Command
Address
t DQSS (NOM)
t DQSS (MIN)
t DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE-to-PRECHARGE – Interrupting
Bank a,
Notes:
WRITE
Col b
T0
t DQSS
t DQSS
t DQSS
1. DI b = data-in for column b.
2. Subsequent element of data-in is applied in the programmed order following DI b.
3. An interrupted burst of 8 is shown; two data elements are written.
4.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T4 and T4n (nominal case) to register DM.
7. If the burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
t
DI
b
WR is referenced from the first positive CK edge after the last data-in pair.
NOP
DI
T1
b
DI
b
T1n
NOP
T2
T2n
t WR
81
NOP
T3
T3n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(a or all)
Bank,
PRE
T4
512Mb: x4, x8, x16 DDR SDRAM
T4n
Transitioning Data
T5
NOP
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t RP
T6
NOP
Operations
Don’t Care