MT47H32M16HR-25E IT:G Micron Technology Inc, MT47H32M16HR-25E IT:G Datasheet - Page 78

• Manufacturer Part Number: MT47H32M16HR-25E IT:G
• Description: 32MX16 DDR2 SDRAM PLASTIC IND TEMP PBF FBGA 1.8V
• Manufacturer: Micron Technology Inc

Specifications of MT47H32M16HR-25E IT:G

• Lead Free Status / Rohs Status: Compliant

CAS Latency (CL)
Figure 35: CL
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. Q 10/10 EN
Notes:
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 34 (page 75). CL is
the delay, in clock cycles, between the registration of a READ command and the availa-
bility of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending
on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be
used as an unknown operation otherwise incompatibility with future versions may result.
DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This fea-
ture allows the READ command to be issued prior to
internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in
further detail in Posted CAS Additive Latency (AL) (page 81).
Examples of CL = 3 and CL = 4 are shown in Figure 35; both assume AL = 0. If a READ
command is registered at clock edge n, and the CL is m clocks, the data will be available
nominally coincident with clock edge n + m (this assumes AL = 0).
DQS, DQS#
DQS, DQS#
Command
Command
1. BL = 4.
2. Posted CAS# additive latency (AL) = 0.
3. Shown with nominal
CK#
CK#
DQ
DQ
CK
CK
READ
READ
T0
T0
NOP
NOP
T1
T1
CL = 3 (AL = 0)
t
AC,
78
t
DQSCK, and
CL = 4 (AL = 0)
NOP
NOP
T2
T2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DQSQ.
512Mb: x4, x8, x16 DDR2 SDRAM
NOP
NOP
T3
T3
DO
n
t
RCD (MIN) by delaying the
n + 1
DO
NOP
NOP
T4
T4
Mode Register (MR)
n + 2
DO
DO
n
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Transitioning data
n + 1
n + 3
DO
DO
NOP
NOP
T5
T5
n + 2
DO
n + 3
DO
NOP
NOP
Don’t care
T6
T6