72210L25TP Integrated Device Technology (Idt), 72210L25TP Datasheet - Page 2

• Manufacturer Part Number: 72210L25TP
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 512 x 8 28-Pin PDIP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72210L25TP

• Package: 28PDIP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 4 Kb
• Organization: 512x8
• Data Bus Width: 8 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

PIN CONFIGURATION
PIN DESCRIPTIONS
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
D
RS
WCLK
WEN
Q
RCLK
REN
OE
EF
AE
AF
FF
V
GND
Symbol
CC
0
0
- D
- Q
7
7
Data Inputs
Reset
Write Clock
Write Enable
Data Outputs
Read Clock
Read Enable
Output Enable
Empty Flag
Almost-Empty Flag
Almost-Full Flag
Full Flag
Power
Ground
Name
O
O
O
O
O
I/O
I
I
I
I
I
I
I
Data inputs for a 8-bit bus.
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and AF go
HIGH, and AE and EF go LOW. A reset is required before an initial WRITE after power-up.
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when WEN is asserted.
When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. Data will not be written
into the FIFO if the FF is LOW.
Data outputs for a 8-bit bus.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted.
When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from
the FIFO if the EF is LOW.
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
state.
When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO
is not empty. EF is synchronized to RCLK.
When AE is LOW, the FIFO is almost empty based on the offset Empty+7. AE is synchronized to RCLK.
When AF is LOW, the FIFO is almost full based on the offset Full-7. AF is synchronized to WCLK.
When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not
full. FF is synchronized to WCLK.
One +5 volt power supply pin.
One 0 volt ground pin.
RCLK
GND
REN
OE
AE
Q0
D4
D3
D2
D1
D0
AF
EF
FF
PLASTIC THIN DIP (P28-2, order code: TP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
2
Description
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2680 drw02
D5
D6
D7
RS
WEN
WCLK
VCC
Q7
Q6
Q5
Q4
Q3
Q2
Q1
COMMERCIAL TEMPERATURE RANGE
JANUARY 8, 2009