72V255LA15PF Integrated Device Technology (Idt), 72V255LA15PF Datasheet - Page 22

• Manufacturer Part Number: 72V255LA15PF
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 8K x 18 64-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V255LA15PF

• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 144 Kb
• Organization: 8Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

NOTE:
1. OE = LOW
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
D
Q
WCLK
RCLK
In IDT Standard mode: D = 8,192 for the IDT72V255LA and 16,384 for the IDT72V265LA.
In FWFT mode: D = 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA.
rising edge of RCLK and the rising edge of WCLK is less than t
0
WEN
0
WCLK
REN
SKEW2
PAF
- D
RCLK
- Q
WEN
REN
LD
15
LD
15
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
t
CLKH
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENS
t
CLKL
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
D - (m+1) words in FIFO
t
ENH
DATA IN OUTPUT
t
REGISTER
CLKH
t
CLKH
1
(2)
t
SKEW2
CLK
t
CLK
t
, then the PAF deassertion time may be delayed one extra WCLK cycle.
t
ENS
LDS
t
t
CLKL
DS
t
t
ENS
LDS
t
CLKL
OFFSET
PAE
2
22
t
PAF
t
t
t
ENH
DH
LDH
t
t
LDH
t
ENH
A
t
ENS
t
SKEW2
(3)
OFFSET
PAF
t
ENH
D - m words in FIFO
OFFSET
PAE
t
1
t
DH
t
ENH
LDH
t
t
LDH
ENH
t
A
COMMERCIAL AND INDUSTRIAL
(2)
TEMPERATURE RANGES
PAF
2
). If the time between the
OCTOBER 22, 2008
t
PAF
OFFSET
PAF
D-(m+1) words
in FIFO
4672 drw 19
4672 drw 17
4672 drw 18
(2)