72V255LA15PFI Integrated Device Technology (Idt), 72V255LA15PFI Datasheet - Page 11

• Manufacturer Part Number: 72V255LA15PFI
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 8K x 18 64-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V255LA15PFI

• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 144 Kb
• Organization: 8Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: -40 to 85 °C

Retransmit setup by setting OR HIGH. During this period, the internal read
pointer is set to the first location of the RAM array.
contents of the first location appear on the outputs. Since FWFT mode is
selected, the first word appears on the outputs, no LOW on REN is
necessary. Reading all subsequent words requires a LOW on REN to
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
8,192 x 18, 16,384 x 18
If FWFT mode is selected, the FIFO will mark the beginning of the
When OR goes LOW, Retransmit setup is complete; at the same time, the
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and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
synchronized to RCLK, thus on the second rising edge of RCLK after RT is
setup, the PAE flag will be updated. HF is asynchronous, thus the rising
edge of RCLK that RT is setup will update HF. PAF is synchronized to
WCLK, thus the second rising edge of WCLK that occurs t
rising edge of RCLK that RT is setup will update PAF. RT is synchronized to
RCLK.
For either IDT Standard mode or FWFT mode, updating of the PAE, HF
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
SKEW
after the