72V255LA20PF Integrated Device Technology (Idt), 72V255LA20PF Datasheet - Page 21

• Manufacturer Part Number: 72V255LA20PF
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 8K x 18 64-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V255LA20PF

• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 144 Kb
• Organization: 8Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D –2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
3. OE = LOW
4. W
5. OR goes LOW at 60 ns + 2 RCLK cycles + t
WCLK
NOTE:
1. X = 12 for the IDT72V255LA and X = 13 for the IDT72V265LA.
8,192 x 18, 16,384 x 18
Q
WCLK
procedure. D = 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA.
SEN
RCLK
0
WEN
REN
LD
1
PAE
PAF
- Q
SI
, W
OR
RT
HF
2
n
, W
t
3
ENS
= first, second and third words written to the FIFO after Master Reset.
W
x
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENH
BIT 0
t
t
LDS
t
ENS
DS
t
ENS
t
RTS
t
RTS
REF
t
t
ENH
LDH
.
EMPTY OFFSET
t
t
REF
t
ENH
HF
t
SKEW4
1
Figure 12. Retransmit Timing (FWFT Mode)
2
t
PAF
1
W
x+1
BIT X
21
(1)
BIT 0
2
t
PAE
FULL OFFSET
3
COMMERCIAL AND INDUSTRIAL
t
A
t
ENH
t
REF
(5)
TEMPERATURE RANGES
W
1
(4)
BIT X
OCTOBER 22, 2008
t
t
t
t
LDH
LDH
LDH
ENH
(1)
W
4
2
t
A
4672 drw 16
t
ENH
4672 drw15
W
3