N25Q128A13BSF40G NUMONYX, N25Q128A13BSF40G Datasheet - Page 139

• Manufacturer Part Number: N25Q128A13BSF40G
• Description: SERIAL NOR
• Manufacturer: NUMONYX

9.3.8
Figure 78. Program OTP instruction sequence QIO-SPI
Subsector Erase (SSE)
For devices with a dedicated part number, at the bottom (or top) of the addressable area
there are 8 boot sectors, each one having 16 4Kbytes subsectors. (See
Ordering
the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must
previously have been executed.
Apart form the parallelizing of the instruction code and the address on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Subsector Erase
(SSE) instruction of the Extended SPI protocol, please refer to
Erase (SSE)
S
C
DQ0
DQ2
DQ3
DQ1
information.) The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside
Instruction
for further details.
0
1
20 16 12 8
21 17 13 9
22 18 14 10
23 19 15 11 7
2
24-Bit Address
3
4
5
6
6
5
4
7
2
1
0
3
8
6
byte1
4
5
7
Data
9 10 11 12 13 14
2
0
1
3
5
6
4
7
byte 2
Data
1
2
3
0
Quad_Program_OTP
Section 9.1.17: Subsector
byte n
5
6
4
7
Data
1
2
0
3
Section 16:
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