C8051F066-GQ Silicon Laboratories Inc, C8051F066-GQ Datasheet
C8051F066-GQ
Manufacturer Part Number
C8051F066-GQ
Description
MCU 8-Bit C8051F06x 8051 CISC 32KB Flash 3.3V 100-Pin TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F06xr
Specifications of C8051F066-GQ
Package
100TQFP
Device Core
8051
Family Name
C8051F06x
Maximum Speed
25 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
59
Interface Type
I2C/SMBus/SPI/UART
On-chip Adc
2-chx16-bit
Number Of Timers
5
Ram Size
4.25 KB
Program Memory Size
32 KB
Program Memory Type
Flash
Operating Temperature
-40 to 85 °C
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
59
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
336-1221
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F066-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F066-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Analog Peripherals
Two 16-Bit ADCs
-
-
-
-
-
Three Comparators
-
-
Internal Voltage Reference
Precision V
On-Chip JTAG Debug & Boundary Scan
-
-
-
-
-
Precision Mixed Signal
CNVSTR0
CNVSTR1
±0.75 LSB INL; no missing codes
Programmable throughput up to 1 Msps (each ADC)
1 external input each; programmable as two single-ended or one differ-
ential ADC
DMA to XRAM or external memory interface
Data-dependent windowed interrupt generator
16 programmable hysteresis values
Configurable to generate interrupts or reset
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints, stack monitor
Inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
IEEE1149.1 compliant boundary scan
VRGND0
VBGAP0
VRGND1
VBGAP1
MONEN
ADGND
XTAL1
XTAL2
VREF0
VREF1
AIN0G
AIN1G
DGND
DGND
DGND
AGND
AGND
AGND
AVDD
VREF
/RST
AIN0
AIN1
TMS
TDO
VDD
VDD
VDD
TCK
AV+
AV+
AV+
TDI
DD
Monitor/Brown-out Detector
VDD Monitor
Digital Power
Analog Power
25 MHz 2%
Oscillator
Oscillator
External
Internal
Circuit
JTAG
Logic
VREF
ADGND
AVDD
Boundary Scan
WDT
Debug HW
(16-Bit)
(16-Bit)
1 Msps
1 Msps
25 MIPS, 32 kB Flash, 16-Bit ADC, 100-Pin Mixed-Signal MCU
ADC0
ADC1
System Clock
R
E
S
U
L
T
0
R
E
S
U
L
T
1
Reset
Copyright © 2004 by Silicon Laboratories
Σ
+
-
C
o
8
0
5
1
e
r
D
F
F
I
External Data
Memory Bus
DMA
256 Byte
FLASH
SFR Bus
32 kB
RAM
RAM
4 kB
High-Speed 8051 µC Core
-
-
-
Memory
-
-
-
Digital Peripherals
-
-
-
-
-
-
Clock Sources
-
-
-
Supply Voltage: 2.7 to 3.6 V
-
-
100-Pin TQFP
Temperature Range: –40 to +85 °C
EMIF
Cntrl
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz system clock
Expanded interrupt handler
4352 bytes data RAM
32 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes
are reserved)
External parallel data memory interface
59 port I/O; all are 5 V tolerant
Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial
ports available concurrently
Programmable 16-bit counter/timer array with six capture/compare mod-
ules
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode using timers or PCA
Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
External oscillator: Crystal, RC, C, or Clock
Can switch between clock sources on-the-fly
Typical operating current: 18 mA at 25 MHz
Multiple power saving sleep and shutdown modes
Timers 0,
SPI Bus
Latches
UART0
UART1
1, 2,3,4
P0, P1,
SMBus
P2, P3
PCA
Bus Control
Address Bus
Data Bus
CP1
Data Latch
Ctrl Latch
C
R
O
S
S
B
A
R
Addr15-8
P4 Latch
P5 Latch
P6 Latch
P7 Latch
CP0
CP2
Addr7-0
+
C8051F066
-
+
+
-
-
P0
Drv
P1
Drv
P2
Drv
P3
Drv
P2.2
P2.3
P2.6
P2.7
P2.4
P2.5
DRV
DRV
DRV
DRV
P4
P5
P6
P7
P0.0
P0.7
P1.0/AIN2.0
P1.7/AIN2.7
P2.0
P2.7
P3.0
P3.7
P4.5
P4.6
P4.7
P5.0
P5.7
P6.0
P6.7
P7.0
P7.7
7.28.04
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C8051F066-GQ Summary of contents
Page 1
... Reset SFR Bus 1, 2,3,4 P0, P1, P2 Latches 32 kB FLASH o 256 Byte r RAM RAM External Data Memory Bus Bus Control EMIF + D Cntrl Σ I DMA Copyright © 2004 by Silicon Laboratories C8051F066 P0.0 P0 Drv P0 P1.0/AIN2 Drv P1.7/AIN2 P2 Drv P2 P3.0 P3 Drv P3.7 P2.6 CP0 + P2.7 - P2.2 ...
Page 2
... 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 0. 16. 14. 0. 16. 14. Copyright © 2004 by Silicon Laboratories C8051F066 TYP MAX UNITS 3 0 µA 0.1 µA 25 MHz 16 bits ±0.75 ±2 LSB LSB ±0.50 ±1 ±0.5 ±1 LSB 103 104 dB 1 Msps V V ...