ZY7120L-T2 POWER ONE, ZY7120L-T2 Datasheet - Page 20

• Manufacturer Part Number: ZY7120L-T2
• Description: Module DC-DC 1-OUT 0.5V to 5.5V 20A 25-Pin SMT T/R
• Manufacturer: POWER ONE
• Type: Step Downr

Specifications of ZY7120L-T2

• Package: 25SMT
• Output Current: 20 A
• Output Voltage: 0.5 to 5.5 V
• Input Voltage: 3 to 13.2 V
• Number Of Outputs: 1

If the falling slew rate control is not utilized, the turn-
off delay only determines an interval from the
application of the Turn-Off command until both high
side and low side switches are turned off. In this
case, the output voltage ramp-down process is
determined by load parameters.
8.2.3
The output voltage tracking is accomplished by
programming the rising and falling slew rates of the
output voltage. To achieve programmed slew rates,
the output voltage is being changed in 12.5mV steps
where duration of each step determines the slew
rate. For example, ramping up a 1.0V output with a
slew rate of 0.5V/ms will require 80 steps duration of
25μs each.
Duration of each voltage step is calculated by
dividing the master clock frequency generated by the
DPM.
synchronized to the master clock, the matching of
voltage slew rates of different outputs is very
accurate as it can be seen in Figure 11 and Figure
16.
During the turn on process, a POL not only delivers
current required by the load (I
the load capacitance. The charging current can be
determined from the equation below:
Where, C
voltage slew rate, and I
When selecting the rising slew rate, a user needs to
ensure that
Where I
the ZY7120. If the condition is not met, then the
overcurrent protection will be triggered during the
turn-on process.
overcurrent
programmed to meet the condition above.
ZD-00194 Rev. 2.5, 01-Jul-10
OCP
Rising and Falling Slew Rates
LOAD
Since all POLs in the system are
is the overcurrent protection threshold of
protection
is load capacitance, dV
I
CHG
I
LOAD
To avoid this, dV

C
CHG

LOAD
I
CHG
is charging current.
threshold


LOAD
dV
I
OCP
R
), but also charges
dt
R
www.power-one.com
R
should
/dt and the
/dt is rising
ZY7120 20A DC-DC Intelligent POL Data Sheet
be
3V to 13.2V Input
8.3
ZY7120 Series converters have a comprehensive set
of programmable protections. The set includes the
output
overcurrent protection, overtemperature protection,
tracking protection, overtemperature warning, and
Power Good signal. Status of protections is stored in
the ST register shown in Figure 37.
Thresholds of overcurrent, over- and undervoltage
protections,
programmed in the GUI Output Configuration
window or directly via the I
CLS and PC2 registers shown in Figure 38 and
Figure 39.
Bit 7
Bit 6:4 R[2:0]: Value of Vo rising slope
Bit 3
Bit 2:0 F[2:0]: Value of Vo falling slope
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note:
- An activated warning/fault/error is encoded as ‘0’
Bit 7
Bit 7
R-1
TP
---
U
Figure 36. Tracking Configuration Register TC
Protections
Unimplemented , read as ‘0’
0: corresponds to 0.1V/ms (default)
1: corresponds to 0.2V/ms
2: corresponds to 0.5V/ms
3: corresponds to 1.0V/ms
4: corresponds to 2.0V/ms
5: corresponds to 5.0V/ms
6: corresponds to 8.3V/ms
7: corresponds to 8.3V/ms
SC, Slew rate control at turn-off
0: Slew rate control is disabled
1: Slew rate control is enabled
0: corresponds to -0.1V/ms (default)
1: corresponds to -0.2V/ms
2: corresponds to -0.5V/ms
3: corresponds to -1.0V/ms
4: corresponds to -2.0V/ms
5: corresponds to -5.0V/ms
6: corresponds to –8.3V/ms
7: corresponds to –8.3V/ms
TP: Temperature Warning
PG: Power Good Warning
TR: Tracking Fault
OT: Overtemperature Fault
OC: Overcurrent Fault
UV: Undervoltage Fault
OV: Overvoltage Error
PV: Phase Voltage Error
Figure 37. Protection Status Register ST
over-
R/W-0
R-0
PG
R2
and
R/W-0
R-1
R1
TR
and
Power

R/W-0
R-1
R0
OT
0.5V to 5.5V Output
undervoltage
2
C bus by writing into the
R/W-1
Good
R-1
SC
OC
Page 20 of 34
R/W-0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
R-1
F2
UV
limits
read as ‘0’
read as ‘0’
R/W-0
protections,
R-1
F1
OV
can
R/W-0
Bit 0
Bit 0
R-1
F0
PV
be