M4A3-128/64-7VNC LATTICE SEMICONDUCTOR, M4A3-128/64-7VNC Datasheet - Page 13

• Manufacturer Part Number: M4A3-128/64-7VNC
• Description: CPLD ispMACH™ 4A Family 5K Gates 128 Macro Cells 105MHz/125MHz EECMOS Technology 3.3V 100-Pin TQFP Tray
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of M4A3-128/64-7VNC

• Package: 100TQFP
• Family Name: ispMACH™ 4A
• Device System Gates: 5000
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 64
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 105|125 MHz
• Number Of Product Terms Per Macro: 20
• Operating Temperature: 0 to 70 °C

A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing
flexibility. In asynchronous mode (Figure 8), a single individual product term is provided for initialization.
It can be selected to control reset or preset.
Note that the reset/preset swapping selection feature effects power-up reset as well. The initialization
functionality of the flip-flops is illustrated in Table 9. The macrocell sends its data to the output switch
matrix and the input switch matrix. The output switch matrix can route this data to an output if so desired.
The input switch matrix can send the signal back to the central switch matrix as feedback.
Note:
1. Transparent latch is unaffected by AR, AP
Product Term
Individual
Reset
Power-Up
a. Reset
Reset
Figure 8. Asynchronous Mode Initialization Configurations
D/L/T
AR
0
0
1
1
AP
Table 9. Asynchronous Reset/Preset Operation
AR
Q
ispMACH 4A Family
17466G-014
AP
0
1
0
1
Product Term
CLK/LE
Individual
X
X
X
X
Preset
1
Power-Up
See Table 8
Preset
Q+
1
0
0
b. Preset
D/L/T
AP
AR
Q
17466G-015
13