XC2C256-6TQ144C Xilinx Inc, XC2C256-6TQ144C Datasheet - Page 7
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XC2C256-6TQ144C
Manufacturer Part Number
XC2C256-6TQ144C
Description
CPLD CoolRunner™-II Family 6K Gates 256 Macro Cells 256MHz 0.18um (CMOS) Technology 1.8V 144-Pin TQFP EP
Manufacturer
Xilinx Inc
Datasheet
1.XC2C32A-6QFG32C.pdf
(16 pages)
Specifications of XC2C256-6TQ144C
Package
144TQFP EP
Family Name
CoolRunnerÂ-II
Device System Gates
6000
Number Of Macro Cells
256
Maximum Propagation Delay Time
6 ns
Number Of User I/os
118
Number Of Logic Blocks/elements
16
Typical Operating Supply Voltage
1.8 V
Maximum Operating Frequency
256 MHz
Number Of Product Terms Per Macro
40
Operating Temperature
0 to 70 °C
Available stocks
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Quantity
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Company:
Part Number:
XC2C256-6TQ144C
Manufacturer:
XILINX
Quantity:
442
Output Banking
CPLDs are widely used as voltage interface translators. To
that end, the output pins are grouped in large banks. The
XC2C32A, XC2C64A, XC2C128 and XC2C256 devices
support two output banks. With two, the outputs switch to
one of two selected output voltage levels, unless both banks
are set to the same voltage. The larger parts (384 and 512
macrocell) support four output banks split evenly. They can
support groupings of one, two, three, or four separate output
voltage levels. This kind of flexibility permits easy interfacing
to 3.3V, 2.5V, 1.8V, and 1.5V in a single part.
DataGATE
Low power is the hallmark of CMOS technology. Other
CPLD families use a sense amplifier approach to creating
product terms, which always has a residual current compo-
nent being drawn. This residual current can be several hun-
dred milliamps, making them unusable in portable systems.
CoolRunner-II CPLDs use standard CMOS methods to cre-
ate the CPLD architecture and deliver the corresponding
low current consumption, without doing any special tricks.
However, sometimes designers want to reduce their system
current even more by selectively disabling circuitry not
being used.
The patented DataGATE technology to permits a straight-
forward approach to additional power reduction. Each I/O
pin has a series switch that can block the arrival of free run-
ning signals that are not of interest. Signals that serve no
use might increase power consumption, and can be dis-
abled. Users are free to do their design, then choose sec-
tions to participate in the DataGATE function. DataGATE is
a logic function that drives an assertion rail threaded
through the medium and high-density CoolRunner-II CPLD
parts. Designers can select inputs to be blocked under the
control of the DataGATE function, effectively blocking con-
trolled switching signals so they do not drive internal chip
capacitances. Output signals that do not switch are held by
the bus hold feature. Any set of input pins can be chosen to
participate in the DataGATE function.
familiar CMOS I
DS090 (v3.1) September 11, 2008
Product Specification
R
CC
versus switching frequency graph. With
Figure 5
shows the
www.xilinx.com
DataGATE, designers can approach zero power, should
they choose to, in their designs.
Figure 6
drives the DataGATE Assertion Rail. It can have any
desired logic function on it. It can be as simple as mapping
an input pin to the DataGATE function or as complex as a
counter or state machine output driving the DataGATE I/O
pin through a macrocell. When the DataGATE rail is
asserted High, any pass transistor switch attached to it is
blocked. Each pin has the ability to attach to the AIM
through a DataGATE pass transistor, and thus be blocked. A
latch automatically captures the state of the pin when it
becomes blocked. The DataGATE Assertion Rail threads
throughout all possible I/Os, so each can participate if cho-
sen. Note that one macrocell is singled out to drive the rail,
and that macrocell is exposed to the outside world through a
pin, for inspection. If DataGATE is not needed, this pin is an
ordinary I/O.
There are two attributes associated with the DataGATE fea-
ture in CoolRunner-II CPLDs. The first attribute specifies if
an input is affected by DataGATE and the second desig-
nates the DataGATE control signal.
The DataGATE feature is selectable on a per pin basis.
Each input pin that uses DataGATE must be assigned a
DATA_GATE attribute.
The DataGATE assertion rail can be driven from either an
I/O pin or internal logic. The DataGATE enable signal is a
dedicated DGE/I/O pin for each package in CoolRunner-II
CPLDs. Upon implementation, the software recognizes a
design using DataGATE and automatically assigns this I/O
pin to the DataGATE enable control function, DGE. Inter-
Figure 5: CMOS I
shows how DataGATE basically works. One I/O pin
I
CC
0
CC
vs. Switching Frequency Curve
Frequency
CoolRunner-II CPLD Family
DS090_05_101001
7