XC2C256-7TQ144C Xilinx Inc, XC2C256-7TQ144C Datasheet - Page 8
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XC2C256-7TQ144C
Manufacturer Part Number
XC2C256-7TQ144C
Description
CPLD CoolRunner™-II Family 6K Gates 256 Macro Cells 152MHz 0.18um (CMOS) Technology 1.8V 144-Pin TQFP EP
Manufacturer
Xilinx Inc
Datasheet
1.XC2C32A-6QFG32C.pdf
(16 pages)
Specifications of XC2C256-7TQ144C
Package
144TQFP EP
Family Name
CoolRunnerÂ-II
Device System Gates
6000
Number Of Macro Cells
256
Maximum Propagation Delay Time
7.5 ns
Number Of User I/os
118
Number Of Logic Blocks/elements
16
Typical Operating Supply Voltage
1.8 V
Maximum Operating Frequency
152 MHz
Number Of Product Terms Per Macro
40
Operating Temperature
0 to 70 °C
Case
TQFP144
Dc
05+
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC2C256-7TQ144C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
CoolRunner-II CPLD Family
nally generated DataGATE control logic can be assigned to
this I/O pin with the BUFG=DATA_GATE attribute.
Global Signals
Global signals, clocks (GCK), sets/resets (GSR), and output
enables (GTS), are designed to strongly resemble each
other. This approach enables design software to make the
best utilization of their capabilities. Each global capability is
supplemented by a corresponding product term version.
Figure 7
trees. The pin input is buffered, then drives multiple internal
global signal traces to deliver low skew and reduce loading
delays. GCK, GSR, and GTS can also be used as general
8
shows the common structure of the global signal
Figure 6: DataGATE Architecture (output drivers not shown)
Latch
Latch
To AIM
To AIM
MC16
MC16
MC1
MC2
MC1
MC2
PLA
PLA
DataGATE Assertion Rail
www.xilinx.com
AIM
purpose I/Os if they are not needed as global signals. The
DataGATE assertion rail is also a global signal.
Figure 7: Global Clocks (GCK), Sets/Resets (GSR), and
PLA
PLA
MC16
MC16
MC1
MC2
MC1
MC2
Output Enables (GTS)
To AIM
To AIM
To AIM
DS090 (v3.1) September 11, 2008
Latch
Latch
Latch
DS090_07_101001
Product Specification
DS090_06_111201
R