XC2C512-10FT256I Xilinx Inc, XC2C512-10FT256I Datasheet - Page 2

• Manufacturer Part Number: XC2C512-10FT256I
• Description: CPLD CoolRunner™-II Family 12K Gates 512 Macro Cells 128MHz 0.18um (CMOS) Technology 1.8V 256-Pin FTBGA
• Manufacturer: Xilinx Inc

Specifications of XC2C512-10FT256I

• Package: 256FTBGA
• Family Name: CoolRunner™-II
• Device System Gates: 12000
• Number Of Macro Cells: 512
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 212
• Number Of Logic Blocks/elements: 32
• Typical Operating Supply Voltage: 1.8 V
• Maximum Operating Frequency: 128 MHz
• Number Of Product Terms Per Macro: 40
• Operating Temperature: -40 to 85 °C

XC2C512 CoolRunner-II CPLD
By mapping a signal to the DataGATE function, lower power
can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O bank-
ing. Four I/O banks are available on the CoolRunner-II 512
macrocell device that permits easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
The CoolRunner-II 512 macrocell CPLD is I/O compatible
with various JEDEC I/O standards (see
device is also 1.5V I/O compatible with the use of
Schmitt-trigger inputs.
RealDigital Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
RealDigital, a design technique that makes use of CMOS
technology in both the fabrication and design methodology.
RealDigital design technology employs a cascade of CMOS
gates to implement sum of products instead of traditional
sense amplifier methodology. Due to this technology, Xilinx
CoolRunner-II CPLDs achieve both high-performance and
low power operation.
Supported I/O Standards
The CoolRunner-II 512 macrocell features LVCMOS,
LVTTL, SSTL, and HSTL I/O implementations. See
Table 2: I
2
Notes:
1.
Typical I
16-bit up/down, Resetable binary counter (one counter per function block).
CC
CC
(mA)
vs Frequency (LVCMOS 1.8V T
150
250
200
100
50
0
0.025
0
0
20
17.22
20
40
Table
A
Figure 1: I
= 25°C)
34.37
1). This
60
40
Table 1
www.xilinx.com
(1)
Frequency (MHz)
80
CC
52.04
60
vs Frequency
100
for I/O standard voltages. The LVTTL I/O standard is a gen-
eral purpose EIA/JEDEC standard for 3.3V applications that
use an LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
Both HSTL and SSTL I/O standards make use of a V
for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V
I/O compatible with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C512
(1) For information on Vref pins, see XAPP399.
(2) LVCMOS15 requires Schmitt-trigger inputs.
IOSTANDARD
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
HSTL_1
SSTL2_1
SSTL3_1
Frequency (MHz)
Attribute
69.44
120
80
140
(2)
86.85
100
Output
160
V
3.3
3.3
2.5
1.8
1.5
1.5
2.5
3.3
CCIO
105.13
DS096_01_030705
180
120
V
Input
3.3
3.3
2.5
1.8
1.5
1.5
2.5
3.3
CCIO
122.68 140.23
DS096 (v3.2) March 8, 2007
140
Input
V
0.75
1.25
Product Specification
N/A
N/A
N/A
N/A
N/A
(1)
1.5
REF
160
Termination
Voltage V
Board
0.75
1.25
N/A
N/A
N/A
N/A
N/A
1.5
157.78
REF
180
TT
pin
R