XC95108-10TQ100I Xilinx Inc, XC95108-10TQ100I Datasheet - Page 15
![CPLD XC9500 Family 2.4K Gates 108 Macro Cells 66.7MHz 0.5um (CMOS) Technology 5V 100-Pin TQFP](/photos/6/70/67082/100-tqfp_sml.jpg)
XC95108-10TQ100I
Manufacturer Part Number
XC95108-10TQ100I
Description
CPLD XC9500 Family 2.4K Gates 108 Macro Cells 66.7MHz 0.5um (CMOS) Technology 5V 100-Pin TQFP
Manufacturer
Xilinx Inc
Series
XC9500r
Datasheets
1.XC9572XL-10TQG100C.pdf
(1 pages)
2.XC9536-15PCG44C.pdf
(17 pages)
3.XC95108-15TQG100C.pdf
(10 pages)
Specifications of XC95108-10TQ100I
Package
100TQFP
Family Name
XC9500
Device System Gates
2400
Number Of Macro Cells
108
Maximum Propagation Delay Time
10 ns
Number Of User I/os
81
Number Of Logic Blocks/elements
8
Typical Operating Supply Voltage
5 V
Maximum Operating Frequency
66.7 MHz
Number Of Product Terms Per Macro
90
Memory Type
Flash
Operating Temperature
-40 to 85 °C
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
6
Number Of Macrocells
108
Number Of Gates
2400
Number Of I /o
81
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
5V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC95108-10TQ100I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
DS063 (v5.5) June 25, 2007
Product Specification
T
PSU
R
All resources within FB using local Feedback
Setup Time = T
T
T
T
Propagation Delay = T
T
GCK
GSR
GTS
Internal Cycle Time = T
IN
Combinatorial
P-Term Clock
Combinatorial
Combinatorial
Logic
Logic
Path
Logic
(a)
PSU
(e)
(c)
T
Pin Feedback
T
T
T
T
LOGILP
PD
Clock to Out Time = T
PTCK
PTSR
PTTS
LOGI
CNT
D/T Q
D/T Q
Figure 15: Detailed Timing Model
Figure 14: Basic Timing Model
S*T
www.xilinx.com
T
PTA
PCO
PCO
D/T
EC
T
T
SUI
HI
T
T
T
SR
T
PDI
AOI
RAI
F
T
Macrocell
COI
XC9500 In-System Programmable CPLD Family
Setup Time = T
Q
Internal System Cycle Time = T
Combinatorial
Combinatorial
Logic
Logic
SU
T
(b)
OUT
(d)
Clock to Out Time = T
D/T Q
D/T Q
T
SLEW
SYSTEM
DS063_14_110501
DS063_15_110501
T
CO
T
EN
CO
15