XC95144-10TQ100I Xilinx Inc, XC95144-10TQ100I Datasheet - Page 14
![CPLD XC9500 Family 3.2K Gates 144 Macro Cells 66.7MHz 0.5um (CMOS) Technology 5V 100-Pin TQFP](/photos/6/70/67082/100-tqfp_sml.jpg)
XC95144-10TQ100I
Manufacturer Part Number
XC95144-10TQ100I
Description
CPLD XC9500 Family 3.2K Gates 144 Macro Cells 66.7MHz 0.5um (CMOS) Technology 5V 100-Pin TQFP
Manufacturer
Xilinx Inc
Series
XC9500r
Datasheets
1.XC9572XL-10TQG100C.pdf
(1 pages)
2.XC9536-15PCG44C.pdf
(17 pages)
3.XC95144-15TQG100C.pdf
(10 pages)
Specifications of XC95144-10TQ100I
Package
100TQFP
Family Name
XC9500
Device System Gates
3200
Number Of Macro Cells
144
Maximum Propagation Delay Time
10 ns
Number Of User I/os
81
Number Of Logic Blocks/elements
8
Typical Operating Supply Voltage
5 V
Maximum Operating Frequency
66.7 MHz
Number Of Product Terms Per Macro
90
Memory Type
Flash
Operating Temperature
-40 to 85 °C
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
144
Number Of Gates
3200
Number Of I /o
81
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
5V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC95144-10TQ100I
Manufacturer:
XILINX
Quantity:
760
Part Number:
XC95144-10TQ100I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
XC9500 In-System Programmable CPLD Family
Low Power Mode
All XC9500 devices offer a low-power mode for individual
macrocells or across all macrocells. This feature allows the
device power to be significantly reduced.
Each individual macrocell may be programmed in
low-power mode by the user. Performance-critical parts of
the application can remain in standard power mode, while
other parts of the application may be programmed for
low-power operation to reduce the overall power dissipa-
tion. Macrocells programmed for low-power mode incur
additional delay (T
well as register setup time. Product term clock to output and
product term output enable delays are unaffected by the
macrocell power-setting.
Timing Model
The uniformity of the XC9500 architecture allows a simpli-
fied timing model for the entire device. The basic timing
14
Figure 13: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
LP
) in pin-to-pin combinatorial delay as
(a)
www.xilinx.com
model, shown in
that use the direct product terms only, with standard power
setting, and standard slew rate setting.
each of the key timing parameters is affected by the product
term allocator (if needed), low-power setting, and slew-lim-
ited setting.
The product term allocation time depends on the logic span
of the macrocell function, which is defined as one less than
the maximum number of allocators in the product term path.
If only direct product terms are used, then the logic span is
0. The example in
terms are available with a span of 1. In the case of
the 18 product term function has a span of 2.
Detailed timing information may be derived from the full tim-
ing model shown in
for each parameter are given in the individual device data
sheets.
Figure
Figure
Figure 6
(b)
14, is valid for macrocell functions
15. The values and explanations
shows that up to 15 product
DS063 (v5.5) June 25, 2007
Product Specification
X5902
Table 4
shows how
Figure
7,
R