LFXP3C-3QN208C LATTICE SEMICONDUCTOR, LFXP3C-3QN208C Datasheet - Page 10

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LFXP3C-3QN208C

Manufacturer Part Number
LFXP3C-3QN208C
Description
FPGA LatticeXP Family 3000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet

Specifications of LFXP3C-3QN208C

Package
208PQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
136
Ram Bits
55296

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0
Lattice Semiconductor
Figure 2-5. Primary Clock Sources
Secondary Clock Sources
LatticeXP devices have four secondary clock resources per quadrant. The secondary clock branches are tapped at
every PFU. These secondary clock networks can also be used for controls and high fanout data. These secondary
clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-6.
Clock Input
PLL Input
PLL Input
Note: Smaller devices have two PLLs.
PLL
PLL
From Routing
From Routing
To Quadrant Clock Selection
20 Primary Clock Sources
Clock Input
Clock Input
2-7
From Routing
From Routing
LatticeXP Family Data Sheet
PLL
PLL
PLL Input
Clock Input
PLL Input
Architecture

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