XC2S100E-6FT256I Xilinx Inc, XC2S100E-6FT256I Datasheet - Page 73

• Manufacturer Part Number: XC2S100E-6FT256I
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 256-Pin FTBGA
• Manufacturer: Xilinx Inc

Specifications of XC2S100E-6FT256I

• Package: 256FTBGA
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 182
• Ram Bits: 40960

FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
DS077-4 (2.3) June 18, 2008
Product Specification
TMS
I/O
I/O
I/O
I/O, L#P_Y
I/O, L#N_Y
I/O, L#P_Y
I/O, L#N_Y
I/O
I/O
I/O, L#P_Y
I/O, L#N_Y
I/O, VREF
Bank 7,
L#P_Y
I/O, L#N_Y
I/O
I/O, L#P_Y
I/O, L#N_Y
I/O, L#P_Y
I/O, L#N_Y
Function Bank
Pad Name
R
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
Pin
E4
D3
C2
C1
D2
D1
E2
E3
E1
G5
G4
G3
G2
G1
F5
F4
F3
F2
F1
200E, 300E,
200E, 300E,
200E, 300E,
200E, 300E,
200E, 300E,
200E, 300E,
200E, 300E,
200E, 300E,
200E, 300E,
200E, 300E,
150E, 300E,
150E, 300E,
XC2S150E,
XC2S150E,
XC2S100E,
XC2S100E,
XC2S100E,
XC2S100E,
XC2S150E,
400E, 600E
XC2S150E,
400E, 600E
XC2S150E,
XC2S150E,
XC2S100E,
XC2S100E,
XC2S150E
XC2S150E
Async.
Output
Option
LVDS
400E
400E
600E
600E
600E
600E
400E
400E
600E
600E
-
-
-
-
-
XC2S200E,
400E, 600E
XC2S600E I/O, L82P_Y
Option
300E,
V
All
REF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O, L85P_Y I/O, L111P
I/O, L84P_Y I/O, L110P
I/O, VREF
I/O, L83N
L85N_Y
L84N_Y
L82N_Y
Bank 7,
100E
L83P
TMS
I/O,
I/O,
I/O,
www.xilinx.com
I/O
I/O
I/O
-
-
-
-
-
-
-
I/O, L111N
I/O, L110N
I/O, VREF
L113N_Y
L112N_Y
L109N_Y
L108N_Y
L107N_Y
L113P_Y
L112P_Y
L109P_Y
L108P_Y
L107P_Y
Bank 7,
150E
TMS
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
I/O
I/O
-
-
Device-Specific Pinouts: XC2S
I/O, L114N
I/O, L114P
I/O, VREF
I/O, VREF
L119P_Y
L119N_Y
L118P_Y
L118N_Y
L117P_Y
L117N_Y
L116P_Y
L116N_Y
L115P_Y
L115N_Y
Bank 7,
Bank 7,
200E
TMS
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
I/O
I/O
I/O
I/O
Spartan-IIE FPGA Family: Pinout Tables
-
-
I/O, VREF
I/O, VREF
L119N_Y
L118N_Y
L117N_Y
L116N_Y
L115N_Y
L114N_Y
L119P_Y
L118P_Y
L117P_Y
L116P_Y
L115P_Y
L114P_Y
Bank 7,
Bank 7,
300E
TMS
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
I/O
I/O
I/O
I/O
I/O
I/O
I/O, L118N
I/O, L117N
I/O, L114N
I/O, L117P
I/O, L114P
I/O, VREF
I/O, VREF
L119P_Y
L119N_Y
L116P_Y
L116N_Y
L115P_Y
L115N_Y
Bank 7,
Bank 7,
L118P
400E
TMS
I/O,
I/O,
I/O,
I/O,
I/O,
I/O
I/O
I/O
I/O
I/O
I/O
I/O, L119P
I/O, L119N
I/O, L115P
I/O, L115N
I/O, VREF
I/O, VREF
I/O, VREF
L118N_Y
L117N_Y
L116N_Y
L114N_Y
L118P_Y
L117P_Y
L116P_Y
L114P_Y
Bank 7,
Bank 7,
Bank 7,
600E
TMS
I/O,
I/O,
I/O,
I/O,
I/O,
I/O
I/O
I/O
I/O
I/O
I/O
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